--- /tmp/pp/gcc-2.7.2.2/combine.c	Sun Nov 26 19:32:07 1995
+++ gcc-2.7.2.2/combine.c	Sun Jul 21 18:53:04 1996
@@ -9579,6 +9579,11 @@
 		  || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
 		      < mode_width)))
 	    {
+	      /* LSHIFTRT would make the number unsigned, so we must make
+		 sure the comparison is unsigned afterwards.  */
+	      if (GET_CODE (op0) == LSHIFTRT)
+		code = unsigned_condition (code);
+
 	      const_op <<= INTVAL (XEXP (op0, 1));
 	      op1 = GEN_INT (const_op);
 	      op0 = XEXP (op0, 0);
--- /tmp/pp/gcc-2.7.2.2/config.guess	Wed Jan 29 21:00:30 1997
+++ gcc-2.7.2.2/config.guess	Fri Mar 14 22:46:00 1997
@@ -314,8 +314,13 @@
 	exit 0 ;;
     *:GNU:*:*)
 	echo `echo ${UNAME_MACHINE}|sed -e 's,/.*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'`
-	exit 0 ;;
+	exit 0 ;;    
     *:Linux:*:*)
+	case "${UNAME_MACHINE}" in
+	    arm[2367] | arm250 | arm[67]10 | sa110)
+		UNAME_MACHINE=arm
+		;;
+	esac
 	# The BFD linker knows what the default object file format is, so
 	# first see if it will tell us.
 	ld_help_string=`ld --help 2>&1`
--- /tmp/pp/gcc-2.7.2.2/config.sub	Thu Jun 15 22:01:49 1995
+++ gcc-2.7.2.2/config.sub	Fri Mar 14 00:37:49 1997
@@ -143,9 +143,12 @@
 		echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2
 		exit 1
 		;;
+	arm-* | arm[2367]-* | arm250-* | arm[67]10-* | sa110-*)
+		basic_machine=arm-unknown
+		;;
 	# Recognize the basic CPU types with company name.
 	vax-* | tahoe-* | i[345]86-* | i860-* | m68k-* | m68000-* | m88k-* \
-	      | sparc-* | ns32k-* | fx80-* | arm-* | c[123]* \
+	      | sparc-* | ns32k-* | fx80-* | c[123]* \
 	      | mips-* | pyramid-* | tron-* | a29k-* | romp-* | rs6000-* | power-* \
 	      | none-* | 580-* | cray2-* | h8300-* | i960-* | xmp-* | ymp-* \
 	      | hppa1.0-* | hppa1.1-* | alpha-* | we32k-* | cydra-* | ns16k-* \
--- /tmp/pp/gcc-2.7.2.2/config/arm/arm.h	Mon Aug 28 11:17:11 1995
+++ gcc-2.7.2.2/config/arm/arm.h	Sun Dec 14 14:09:00 1997
@@ -158,7 +158,9 @@
 #define TARGET_DEFAULT  0
 #endif
 
+#ifndef TARGET_MEM_FUNCTIONS
 #define TARGET_MEM_FUNCTIONS 1
+#endif
 
 /* OVERRIDE_OPTIONS takes care of the following:
    - if -mpoke-function-name, then -mapcs.
@@ -334,6 +336,11 @@
                      [|  saved f4 value     |]     three words
   r0-r3 are not normally saved in a C function.  */
 
+#define DYNAMIC_CHAIN_ADDRESS(frame) \
+  gen_rtx(PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, -12))
+#define RETURN_ADDR_RTX(count, frame) \
+  gen_rtx(MEM, Pmode, plus_constant (frame, -4))
+
 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP.  */
 #define FIRST_PSEUDO_REGISTER  27
 
@@ -369,6 +376,9 @@
    XXX Is this still needed?  */
 #define CONDITIONAL_REGISTER_USAGE  \
 {							\
+  if (flag_pic)						\
+    fixed_regs[PIC_OFFSET_TABLE_REGNUM] =		\
+     call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;	\
   if (obey_regdecls)					\
     fixed_regs[0] = 1;					\
   if (TARGET_SOFT_FLOAT)				\
@@ -410,6 +420,10 @@
 /* Specify the registers used for certain standard purposes.
    The values of these macros are register numbers.  */
 
+/* Register to hold the addressing base for position independent
+   code access to data items.  */
+#define PIC_OFFSET_TABLE_REGNUM	10
+
 /* Define this if the program counter is overloaded on a register.  */
 #define PC_REGNUM		15
 
@@ -918,6 +932,18 @@
 	   || neg_const_double_rtx_ok_for_fpu (X)))		\
    || CONSTANT_ADDRESS_P (X))
 
+/* Nonzero if the constant value X is a legitimate general operand
+   when generating PIC code.  It is given that flag_pic is on and
+   that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
+
+#define LEGITIMATE_PIC_OPERAND_P(X)					\
+  (! SYMBOLIC_CONST (X)							\
+     || (GET_CODE (X) == SYMBOL_REF /*&& CONSTANT_POOL_ADDRESS_P (X)*/)	\
+     || CONSTANT_ADDRESS_P (X))
+
+#define SYMBOLIC_CONST(X)       \
+  (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)
+
 /* Symbols in the text segment can be accessed without indirecting via the
    constant pool; it may take an extra binary operation, but this is still
    faster than indirecting via memory.  Don't do this when not optimizing,
@@ -935,6 +961,24 @@
     }									\
 }
 
+/* The `FINALIZE_PIC' macro serves as a hook to emit these special
+   codes once the function is being compiled into assembly code, but
+   not before.  (It is not done before, because in the case of
+   compiling an inline function, it would lead to multiple PIC
+   prologues being included in functions which used inline functions
+   and were compiled to assembly language.)  */
+
+#define FINALIZE_PIC							\
+do									\
+  {									\
+    extern int current_function_uses_pic_offset_table;			\
+									\
+    current_function_uses_pic_offset_table |= profile_flag | 		\
+						profile_block_flag;	\
+    finalize_pic ();							\
+  }									\
+while (0)
+
 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
    and check its validity for a certain class.
    We have two alternate definitions for each of them.
@@ -1040,8 +1084,11 @@
    INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
    Allow REG-only and AUTINC-REG if handling TImode or HImode.  Other symbol
    refs must be forced though a static cell to ensure addressability.  */
+#include <stdio.h>
 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL)  \
 {									\
+if (flag_pic) \
+{fprintf (stderr, "GO_IF_LEGITIMATE_ADDRESS: "); print_rtl (stderr, X); fprintf (stderr, "\n");} \
   if (BASE_REGISTER_RTX_P (X))						\
     goto LABEL;								\
   else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC)	\
@@ -1094,8 +1141,11 @@
    On the ARM, try to convert [REG, #BIGCONST]
    into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
    where VALIDCONST == 0 in case of TImode.  */
+extern struct rtx_def *legitimize_pic_address ();
 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)				 \
 {									 \
+  if (flag_pic)								 \
+    (X) = legitimize_pic_address (X, MODE, 0);				 \
   if (GET_CODE (X) == PLUS)						 \
     {									 \
       rtx xop0 = XEXP (X, 0);						 \
@@ -1153,7 +1203,6 @@
     goto WIN;								 \
 }
 
-
 /* Go to LABEL if ADDR (a legitimate address expression)
    has an effect that depends on the machine mode it is used for.  */
 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)  \
@@ -1199,9 +1248,16 @@
    will either zero-extend or sign-extend.  The value of this macro should
    be the code that says which one of the two operations is implicitly
    done, NIL if none.  */
+#if 0
+#define LOAD_EXTEND_OP(MODE)						\
+  ((MODE) == QImode ? ZERO_EXTEND					\
+   : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND		\
+   : ((!BYTES_BIG_ENDIAN && (MODE) == HImode) ? ZERO_EXTEND : NIL)))
+#else
 #define LOAD_EXTEND_OP(MODE)						\
   ((MODE) == QImode ? ZERO_EXTEND					\
    : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
+#endif
 
 /* Define this if zero-extension is slow (more than one real instruction).
    On the ARM, it is more than one instruction only if not fetching from
@@ -1373,6 +1429,8 @@
 #define ARM_OS_NAME "(generic)"
 #endif
 
+#ifndef ASM_FILE_START
+#ifndef NO_REQ
 /* The text to go at the start of the assembler file */
 #define ASM_FILE_START(STREAM)						  \
 {									  \
@@ -1387,16 +1445,36 @@
   fprintf (STREAM,"%slr\t.req\t%sr14\n", REGISTER_PREFIX, REGISTER_PREFIX); \
   fprintf (STREAM,"%spc\t.req\t%sr15\n", REGISTER_PREFIX, REGISTER_PREFIX); \
 }
+#else
+#define ASM_FILE_START(STREAM)						  \
+{									  \
+  extern char *version_string;						  \
+  fprintf (STREAM,"%s Generated by gcc %s for ARM/%s\n",		  \
+	   ASM_COMMENT_START, version_string, ARM_OS_NAME);		  \
+}
+#endif
+#endif
 
+#ifndef ASM_APP_ON
 #define ASM_APP_ON  ""
+#endif
+
+#ifndef ASM_APP_OFF
 #define ASM_APP_OFF  ""
+#endif
 
 /* Switch to the text or data segment.  */
 #define TEXT_SECTION_ASM_OP  ".text"
 #define DATA_SECTION_ASM_OP  ".data"
 
 #define REGISTER_PREFIX ""
+#ifdef NO_UNDERSCORES
+#define USER_LABEL_PREFIX ""
+#define INTERNAL_LABEL_PREFIX "."
+#else
 #define USER_LABEL_PREFIX "_"
+#define INTERNAL_LABEL_PREFIX ""
+#endif
 #define LOCAL_LABEL_PREFIX ""
 
 /* The assembler's names for the registers.  */
@@ -1445,7 +1523,9 @@
 
 /* Generate DBX debugging information.  riscix.h will undefine this because
    the native assembler does not support stabs. */
+#ifndef DBX_DEBUGGING_INFO
 #define DBX_DEBUGGING_INFO  1
+#endif
 
 /* Acorn dbx moans about continuation chars, so don't use any.  */
 #ifndef DBX_CONTIN_LENGTH
@@ -1467,8 +1547,10 @@
   arm_asm_output_label ((STREAM), (NAME))
 
 /* Output a function label definition.  */
+#ifndef ASM_DECLARE_FUNCTION_NAME
 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
     ASM_OUTPUT_LABEL(STREAM, NAME)
+#endif
 
 /* Output a globalising directive for a label.  */
 #define ASM_GLOBALIZE_LABEL(STREAM,NAME)  \
@@ -1477,12 +1559,18 @@
    fputc ('\n',STREAM))                   \
 
 /* Output a reference to a label.  */
+#ifndef ASM_OUTPUT_LABELREF
 #define ASM_OUTPUT_LABELREF(STREAM,NAME)  \
   fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, NAME)
+#endif
 
 /* Make an internal label into a string.  */
+#ifndef ASM_GENERATE_INTERNAL_LABEL
 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM)  \
   sprintf (STRING, "*%s%d", PREFIX, NUM)
+#endif
+
+#define INTERNAL_LABEL_FORMAT "%s%d"
 
 /* Output an internal label definition.  */
 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM)  \
@@ -1499,7 +1587,7 @@
 	  arm_target_insn = NULL;					\
 	}								\
 	strcpy (s, "*");				      		\
-	sprintf (&s[strlen (s)], "%s%d", (PREFIX), (NUM));   		\
+	sprintf (&s[strlen (s)], INTERNAL_LABEL_FORMAT, (PREFIX), (NUM));\
 	arm_asm_output_label (STREAM, s);		                \
     } while (0)
 
@@ -1528,7 +1616,7 @@
 
 /* Output an element of a dispatch table.  */
 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE)  \
-   fprintf (STREAM, "\t.word\tL%d\n", VALUE)
+   fprintf (STREAM, "\t.word\t.L%d\n", VALUE)
 
 /* Output various types of constants.  For real numbers we output hex, with
    a comment containing the "human" value, this allows us to pass NaN's which
@@ -1640,8 +1728,10 @@
 /* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */
 
 /* Output a #ident directive.  */
+#ifndef ASM_OUTPUT_IDENT
 #define ASM_OUTPUT_IDENT(STREAM,STRING)  \
   fprintf (STREAM,"- - - ident %s\n",STRING)
+#endif
 
 /* The assembler's parentheses characters.  */
 #define ASM_OPEN_PAREN "("
--- /tmp/pp/gcc-2.7.2.2/config/arm/arm.md	Sat Jun 29 17:26:02 1996
+++ gcc-2.7.2.2/config/arm/arm.md	Sun Nov 30 16:33:42 1997
@@ -1287,6 +1287,8 @@
  (set_attr "length" "12")
  (set_attr "type" "store1")])
 
+; Reject the frame pointer in operand[1], since reloading this after
+; it has been eliminated can cause carnage.
 (define_insn ""
   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 	(match_operator:SI 4 "shiftable_operator"
@@ -1295,7 +1297,9 @@
 	    (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
 	  (match_operand:SI 1 "s_register_operand" "0,?r")]))
    (clobber (reg:CC 24))]
-  ""
+  "GET_CODE (operands[1]) != REG
+   || (REGNO(operands[1]) != FRAME_POINTER_REGNUM
+       && REGNO(operands[1]) != ARG_POINTER_REGNUM)"
   "*
 {
   enum rtx_code code = GET_CODE (operands[4]);
@@ -1998,6 +2002,12 @@
         (match_operand:SI 1 "general_operand" ""))]
   ""
   "
+{
+  extern int flag_pic;
+
+  if (flag_pic)
+    arm_movsi_pic (operands, SImode);
+
   /* Everything except mem = const or mem = mem can be done easily */
   if (GET_CODE (operands[0]) == MEM)
     operands[1] = force_reg (SImode, operands[1]);
@@ -2011,7 +2021,7 @@
 			   : preserve_subexpressions_p ()));
       DONE;
     }
-")
+}")
 
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,m,r,r")
--- /tmp/pp/gcc-2.7.2.2/config/arm/lib1funcs-linux.asm	Wed Jan 28 22:29:43 1998
+++ gcc-2.7.2.2/config/arm/lib1funcs-linux.asm	Sun Jul 21 22:03:54 1996
@@ -0,0 +1,1607 @@
+@ libgcc1 routines for ARM cpu.
+@ Division and remainder, from Appendix E of the Sparc Version 8
+@ Architecture Manual, with fixes from Gordon Irlam.
+@ Rewritten for the ARM by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
+
+/* Copyright (C) 1995 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* As a special exception, if you link this library with other files,
+   some of which are compiled with GCC, to produce an executable,
+   this library does not by itself cause the resulting executable
+   to be covered by the GNU General Public License.
+   This exception does not however invalidate any other reasons why
+   the executable file might be covered by the GNU General Public License.  */
+
+/*
+ * Input: dividend and divisor in r0 and r1 respectively.
+ *
+ * m4 parameters:
+ *  NAME	name of function to generate
+ *  OP		OP=div => r0 / r1; OP=mod => r0 % r1
+ *  S		S=true => signed; S=false => unsigned
+ *
+ * Algorithm parameters:
+ *  N		how many bits per iteration we try to get (4)
+ *  WORDSIZE	total number of bits (32)
+ *
+ * Derived constants:
+ *  TOPBITS	number of bits in the top `decade' of a number
+ *
+ * Important variables:
+ *  Q		the partial quotient under development (initially 0)
+ *  R		the remainder so far, initially the dividend
+ *  ITER	number of main division loop iterations required;
+ *		equal to ceil(log2(quotient) / N).  Note that this
+ *		is the log base (2^N) of the quotient.
+ *  V		the current comparand, initially divisor*2^(ITER*N-1)
+ *
+ * Cost:
+ *  Current estimate for non-large dividend is
+ *	ceil(log2(quotient) / N) * (10 + 7N/2) + C
+ *  A large dividend is one greater than 2^(31-TOPBITS) and takes a
+ *  different path, as the upper bits of the quotient must be developed
+ *  one bit at a time.
+ */
+
+/*
+define(N, `4')dnl
+define(WORDSIZE, `32')dnl
+define(TOPBITS, eval(WORDSIZE - N*((WORDSIZE-1)/N)))dnl
+dnl
+define(dividend, `r0')dnl
+define(divisor, `r1')dnl
+define(Q, `r2')dnl
+define(R, `r3')dnl
+define(ITER, `ip')dnl
+define(V, `lr')dnl
+dnl
+dnl m4 reminder: ifelse(a,b,c,d) => if a is b, then c, else d
+define(T, `r4')dnl
+define(SC, `r5')dnl
+ifelse(S, `true', `define(SIGN, `r6')')dnl
+define(REGLIST, `ifelse(S, `true', `{r4, r5, r6,', `{r4, r5,')')dnl
+define(ret, `ldmia	sp!, REGLIST pc}^')dnl
+dnl
+dnl This is the recursive definition for developing quotient digits.
+dnl
+dnl Parameters:
+dnl  $1	the current depth, 1 <= $1 <= N
+dnl  $2	the current accumulation of quotient bits
+dnl  N	max depth
+dnl
+dnl We add a new bit to $2 and either recurse or insert the bits in
+dnl the quotient.  R, Q, and V are inputs and outputs as defined above;
+dnl the condition codes are expected to reflect the input R, and are
+dnl modified to reflect the output R.
+dnl
+define(DEVELOP_QUOTIENT_BITS,
+`	@ depth $1, accumulated bits $2
+	mov	V, V, lsr #1
+	blt	L.$1.eval(2^N+$2+999)
+	@ remainder is positive
+	subs	R, R, V
+	ifelse($1, N,
+	`	ifelse(eval(2*$2+1<0), `0',
+		`add	Q, Q, `#'eval($2*2+1)',
+		`sub	Q, Q, `#'eval(-($2*2+1))')
+
+		b	9f
+	', `	DEVELOP_QUOTIENT_BITS(incr($1), `eval(2*$2+1)')')
+L.$1.eval(2^N+$2+999):
+	@ remainder is negative
+	adds	R, R, V
+	ifelse($1, N,
+	`	ifelse(eval(2*$2-1<0), `0',
+		`add	Q, Q, `#'eval($2*2-1)',
+		`sub	Q, Q, `#'eval(-($2*2-1))')
+		b	9f
+
+	', `	DEVELOP_QUOTIENT_BITS(incr($1), `eval(2*$2-1)')')
+	ifelse($1, 1, `9:')')dnl
+
+#include "trap.h"
+
+ip	.req	r12
+sp	.req	r13
+lr	.req	r14
+pc	.req	r15
+.text
+	.globl NAME
+	.align 0
+NAME:
+	stmdb	sp!, REGLIST lr}
+ifelse(S, `true',
+`	@ compute sign of result; if neither is negative, no problem
+	ifelse(OP, `div', `eor	SIGN, divisor, dividend	@ compute sign',
+		`mov	SIGN, dividend')
+	cmp	divisor, #0
+	rsbmi	divisor, divisor, #0
+	beq	Ldiv_zero
+	mov	V, divisor
+	movs	R, dividend
+	rsbmi	R, R, #0	@ make dividend nonnegative
+',
+`	@ Ready to divide.  Compute size of quotient; scale comparand.
+	movs	V, divisor
+	mov	R, dividend
+	beq	Ldiv_zero
+')
+
+	cmp	R, V			@ if divisor exceeds dividend, done
+	mov	Q, #0
+	bcc	Lgot_result		@ (and algorithm fails otherwise)
+	mov	T, `#'(1 << (WORDSIZE - TOPBITS - 1))
+	cmp	R, T
+	mov	ITER, #0
+	bcc	Lnot_really_big
+
+	@ `Here the dividend is >= 2^(31-N) or so.  We must be careful here,
+	@ as our usual N-at-a-shot divide step will cause overflow and havoc.
+	@ The number of bits in the result here is N*ITER+SC, where SC <= N.
+	@ Compute ITER in an unorthodox manner: know we need to shift V into
+	@ the top decade: so do not even bother to compare to R.'
+		mov	SC, #1
+	1:
+		cmp	V, T
+		bcs	3f
+		mov	V, V, lsl `#'N
+		add	ITER, ITER, #1
+		b	1b
+
+	@ Now compute SC.
+	2:	adds	V, V, V
+		add	SC, SC, #1
+		bcc	Lnot_too_big
+
+		@ We get here if the divisor overflowed while shifting.
+		@ This means that R has the high-order bit set.
+		@ Restore V and subtract from R.
+		mov	T, T, lsl `#'TOPBITS
+		mov	V, V, lsr #1
+		add	V, T, V
+		sub	SC, SC, #1
+		b	Ldo_single_div
+
+	Lnot_too_big:
+	3:	cmp	V, R
+		bcc	2b
+@		beq	Ldo_single_div
+
+	/-* NB: these are commented out in the V8-Sparc manual as well *-/
+	/-* (I do not understand this) *-/
+	@ V > R: went too far: back up 1 step
+	@	srl	V, 1, V
+	@	dec	SC
+	@ do single-bit divide steps
+	@
+	@ We have to be careful here.  We know that R >= V, so we can do the
+	@ first divide step without thinking.  BUT, the others are conditional,
+	@ and are only done if R >= 0.  Because both R and V may have the high-
+	@ order bit set in the first step, just falling into the regular
+	@ division loop will mess up the first time around.
+	@ So we unroll slightly...
+	Ldo_single_div:
+		subs	SC, SC, #1
+		blt	Lend_regular_divide
+		sub	R, R, V
+		mov	Q, #1
+		b	Lend_single_divloop
+	Lsingle_divloop:
+		cmp	R, #0
+		mov	Q, Q, lsl #1
+		mov	V, V, lsr #1
+		@ R >= 0
+		subpl	R, R, V
+		addpl	Q, Q, #1
+		@ R < 0
+		addmi	R, R, V
+		submi	Q, Q, #1
+	Lend_single_divloop:
+		subs	SC, SC, #1
+		bge	Lsingle_divloop
+		b	Lend_regular_divide
+
+1:
+	add	ITER, ITER, #1
+Lnot_really_big:
+	mov	V, V, lsl `#'N
+	cmp	V, R
+	bls	1b
+	@
+	@	HOW CAN ITER EVER BE -1 HERE ?????
+	@
+	cmn	ITER, #1
+	beq	Lgot_result
+
+Ldivloop:
+	cmp	R, #0	@ set up for initial iteration
+	mov	Q, Q, lsl `#'N
+	DEVELOP_QUOTIENT_BITS(1, 0)
+Lend_regular_divide:
+	subs	ITER, ITER, #1
+	bge	Ldivloop
+	cmp	R, #0
+	@ non-restoring fixup here (one instruction only!)
+ifelse(OP, `div',
+`	sublt	Q, Q, #1
+', `	addlt	R, divisor, R
+')
+
+Lgot_result:
+ifelse(S, `true',
+`	@ check to see if answer should be < 0
+	cmp	SIGN, #0
+	ifelse(OP, `div', `rsbmi Q, Q, #0', `rsbmi R, R, #0')
+')
+	ifelse(OP, `div', `mov r0, Q', `mov r0, R')
+	ret
+
+Ldiv_zero:
+	@ Divide by zero trap.  If it returns, return 0 (about as
+	@ wrong as possible, but that is what SunOS does...).
+	bl	___div0
+	mov	r0, #0
+	ret
+*/
+
+#if defined(__arm6__) || defined(__arm7__)
+#define RETPC
+#define MOVPC	mov
+#else
+#define RETPC ^
+#define MOVPC	movs
+#endif
+
+#ifdef L_udivsi3
+
+ip	.req	r12
+sp	.req	r13
+lr	.req	r14
+pc	.req	r15
+.text
+	.globl ___udivsi3
+	.align 0
+___udivsi3:
+	stmdb	sp!, {r4, r5, lr}
+	@ Ready to divide.  Compute size of quotient; scale comparand.
+	movs	lr, r1
+	mov	r3, r0
+	beq	Ldiv_zero
+
+
+	cmp	r3, lr			@ if r1 exceeds r0, done
+	mov	r2, #0
+	bcc	Lgot_result		@ (and algorithm fails otherwise)
+	mov	r4, #(1 << (32 - 4 - 1))
+	cmp	r3, r4
+	mov	ip, #0
+	bcc	Lnot_really_big
+
+	@ Here the dividend is >= 2^(31-N) or so.  We must be careful here,
+	@ as our usual N-at-a-shot divide step will cause overflow and havoc.
+	@ The number of bits in the result here is N*ITER+SC, where SC <= N.
+	@ Compute ITER in an unorthodox manner: know we need to shift V into
+	@ the top decade: so do not even bother to compare to R.
+		mov	r5, #1
+	1:
+		cmp	lr, r4
+		bcs	3f
+		mov	lr, lr, lsl #4
+		add	ip, ip, #1
+		b	1b
+
+	@ Now compute r5.
+	2:	adds	lr, lr, lr
+		add	r5, r5, #1
+		bcc	Lnot_too_big
+
+		@ We get here if the r1 overflowed while shifting.
+		@ This means that r3 has the high-order bit set.
+		@ Restore lr and subtract from r3.
+		mov	r4, r4, lsl #4
+		mov	lr, lr, lsr #1
+		add	lr, r4, lr
+		sub	r5, r5, #1
+		b	Ldo_single_div
+
+	Lnot_too_big:
+	3:	cmp	lr, r3
+		bcc	2b
+@		beq	Ldo_single_div
+
+	/* NB: these are commented out in the V8-Sparc manual as well */
+	/* (I do not understand this) */
+	@ lr > r3: went too far: back up 1 step
+	@	srl	lr, 1, lr
+	@	dec	r5
+	@ do single-bit divide steps
+	@
+	@ We have to be careful here.  We know that r3 >= lr, so we can do the
+	@ first divide step without thinking.  BUT, the others are conditional,
+	@ and are only done if r3 >= 0.  Because both r3 and lr may have the high-
+	@ order bit set in the first step, just falling into the regular
+	@ division loop will mess up the first time around.
+	@ So we unroll slightly...
+	Ldo_single_div:
+		subs	r5, r5, #1
+		blt	Lend_regular_divide
+		sub	r3, r3, lr
+		mov	r2, #1
+		b	Lend_single_divloop
+	Lsingle_divloop:
+		cmp	r3, #0
+		mov	r2, r2, lsl #1
+		mov	lr, lr, lsr #1
+		@ r3 >= 0
+		subpl	r3, r3, lr
+		addpl	r2, r2, #1
+		@ r3 < 0
+		addmi	r3, r3, lr
+		submi	r2, r2, #1
+	Lend_single_divloop:
+		subs	r5, r5, #1
+		bge	Lsingle_divloop
+		b	Lend_regular_divide
+
+1:
+	add	ip, ip, #1
+Lnot_really_big:
+	mov	lr, lr, lsl #4
+	cmp	lr, r3
+	bls	1b
+	@
+	@	HOW CAN ip EVER BE -1 HERE ?????
+	@
+	cmn	ip, #1
+	beq	Lgot_result
+
+Ldivloop:
+	cmp	r3, #0	@ set up for initial iteration
+	mov	r2, r2, lsl #4
+		@ depth 1, accumulated bits 0
+	mov	lr, lr, lsr #1
+	blt	L.1.1015
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 2, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.2.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 3, accumulated bits 3
+	mov	lr, lr, lsr #1
+	blt	L.3.1018
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits 7
+	mov	lr, lr, lsr #1
+	blt	L.4.1022
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #15
+
+		b	9f
+	
+L.4.1022:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #13
+		b	9f
+
+	
+	
+L.3.1018:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits 5
+	mov	lr, lr, lsr #1
+	blt	L.4.1020
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #11
+
+		b	9f
+	
+L.4.1020:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #9
+		b	9f
+
+	
+	
+	
+L.2.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 3, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.3.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits 3
+	mov	lr, lr, lsr #1
+	blt	L.4.1018
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #7
+
+		b	9f
+	
+L.4.1018:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #5
+		b	9f
+
+	
+	
+L.3.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.4.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #3
+
+		b	9f
+	
+L.4.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #1
+		b	9f
+
+	
+	
+	
+	
+L.1.1015:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 2, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.2.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 3, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.3.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.4.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #1
+
+		b	9f
+	
+L.4.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #3
+		b	9f
+
+	
+	
+L.3.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits -3
+	mov	lr, lr, lsr #1
+	blt	L.4.1012
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #5
+
+		b	9f
+	
+L.4.1012:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #7
+		b	9f
+
+	
+	
+	
+L.2.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 3, accumulated bits -3
+	mov	lr, lr, lsr #1
+	blt	L.3.1012
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits -5
+	mov	lr, lr, lsr #1
+	blt	L.4.1010
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #9
+
+		b	9f
+	
+L.4.1010:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #11
+		b	9f
+
+	
+	
+L.3.1012:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits -7
+	mov	lr, lr, lsr #1
+	blt	L.4.1008
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #13
+
+		b	9f
+	
+L.4.1008:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #15
+		b	9f
+
+	
+	
+	
+	
+	9:
+Lend_regular_divide:
+	subs	ip, ip, #1
+	bge	Ldivloop
+	cmp	r3, #0
+	@ non-restoring fixup here (one instruction only!)
+	sublt	r2, r2, #1
+
+
+Lgot_result:
+
+	mov r0, r2
+	ldmia	sp!, {r4, r5, pc} RETPC
+
+Ldiv_zero:
+	@ Divide by zero trap.  If it returns, return 0 (about as
+	@ wrong as possible, but that is what SunOS does...).
+	bl	___div0
+	mov	r0, #0
+	ldmia	sp!, {r4, r5, pc} RETPC
+
+#endif /* L_udivsi3 */
+
+#ifdef L_divsi3
+
+ip	.req	r12
+sp	.req	r13
+lr	.req	r14
+pc	.req	r15
+.text
+	.globl ___divsi3
+	.align 0
+___divsi3:
+	stmdb	sp!, {r4, r5, r6, lr}
+	@ compute sign of result; if neither is negative, no problem
+	eor	r6, r1, r0	@ compute sign
+	cmp	r1, #0
+	rsbmi	r1, r1, #0
+	beq	Ldiv_zero
+	mov	lr, r1
+	movs	r3, r0
+	rsbmi	r3, r3, #0	@ make dividend nonnegative
+
+
+	cmp	r3, lr			@ if r1 exceeds r0, done
+	mov	r2, #0
+	bcc	Lgot_result		@ (and algorithm fails otherwise)
+	mov	r4, #(1 << (32 - 4 - 1))
+	cmp	r3, r4
+	mov	ip, #0
+	bcc	Lnot_really_big
+
+	@ Here the dividend is >= 2^(31-N) or so.  We must be careful here,
+	@ as our usual N-at-a-shot divide step will cause overflow and havoc.
+	@ The number of bits in the result here is N*ITER+SC, where SC <= N.
+	@ Compute ITER in an unorthodox manner: know we need to shift V into
+	@ the top decade: so do not even bother to compare to R.
+		mov	r5, #1
+	1:
+		cmp	lr, r4
+		bcs	3f
+		mov	lr, lr, lsl #4
+		add	ip, ip, #1
+		b	1b
+
+	@ Now compute r5.
+	2:	adds	lr, lr, lr
+		add	r5, r5, #1
+		bcc	Lnot_too_big
+
+		@ We get here if the r1 overflowed while shifting.
+		@ This means that r3 has the high-order bit set.
+		@ Restore lr and subtract from r3.
+		mov	r4, r4, lsl #4
+		mov	lr, lr, lsr #1
+		add	lr, r4, lr
+		sub	r5, r5, #1
+		b	Ldo_single_div
+
+	Lnot_too_big:
+	3:	cmp	lr, r3
+		bcc	2b
+@		beq	Ldo_single_div
+
+	/* NB: these are commented out in the V8-Sparc manual as well */
+	/* (I do not understand this) */
+	@ lr > r3: went too far: back up 1 step
+	@	srl	lr, 1, lr
+	@	dec	r5
+	@ do single-bit divide steps
+	@
+	@ We have to be careful here.  We know that r3 >= lr, so we can do the
+	@ first divide step without thinking.  BUT, the others are conditional,
+	@ and are only done if r3 >= 0.  Because both r3 and lr may have the high-
+	@ order bit set in the first step, just falling into the regular
+	@ division loop will mess up the first time around.
+	@ So we unroll slightly...
+	Ldo_single_div:
+		subs	r5, r5, #1
+		blt	Lend_regular_divide
+		sub	r3, r3, lr
+		mov	r2, #1
+		b	Lend_single_divloop
+	Lsingle_divloop:
+		cmp	r3, #0
+		mov	r2, r2, lsl #1
+		mov	lr, lr, lsr #1
+		@ r3 >= 0
+		subpl	r3, r3, lr
+		addpl	r2, r2, #1
+		@ r3 < 0
+		addmi	r3, r3, lr
+		submi	r2, r2, #1
+	Lend_single_divloop:
+		subs	r5, r5, #1
+		bge	Lsingle_divloop
+		b	Lend_regular_divide
+
+1:
+	add	ip, ip, #1
+Lnot_really_big:
+	mov	lr, lr, lsl #4
+	cmp	lr, r3
+	bls	1b
+	@
+	@	HOW CAN ip EVER BE -1 HERE ?????
+	@
+	cmn	ip, #1
+	beq	Lgot_result
+
+Ldivloop:
+	cmp	r3, #0	@ set up for initial iteration
+	mov	r2, r2, lsl #4
+		@ depth 1, accumulated bits 0
+	mov	lr, lr, lsr #1
+	blt	L.1.1015
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 2, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.2.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 3, accumulated bits 3
+	mov	lr, lr, lsr #1
+	blt	L.3.1018
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits 7
+	mov	lr, lr, lsr #1
+	blt	L.4.1022
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #15
+
+		b	9f
+	
+L.4.1022:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #13
+		b	9f
+
+	
+	
+L.3.1018:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits 5
+	mov	lr, lr, lsr #1
+	blt	L.4.1020
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #11
+
+		b	9f
+	
+L.4.1020:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #9
+		b	9f
+
+	
+	
+	
+L.2.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 3, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.3.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits 3
+	mov	lr, lr, lsr #1
+	blt	L.4.1018
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #7
+
+		b	9f
+	
+L.4.1018:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #5
+		b	9f
+
+	
+	
+L.3.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.4.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #3
+
+		b	9f
+	
+L.4.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #1
+		b	9f
+
+	
+	
+	
+	
+L.1.1015:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 2, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.2.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 3, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.3.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.4.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #1
+
+		b	9f
+	
+L.4.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #3
+		b	9f
+
+	
+	
+L.3.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits -3
+	mov	lr, lr, lsr #1
+	blt	L.4.1012
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #5
+
+		b	9f
+	
+L.4.1012:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #7
+		b	9f
+
+	
+	
+	
+L.2.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 3, accumulated bits -3
+	mov	lr, lr, lsr #1
+	blt	L.3.1012
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits -5
+	mov	lr, lr, lsr #1
+	blt	L.4.1010
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #9
+
+		b	9f
+	
+L.4.1010:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #11
+		b	9f
+
+	
+	
+L.3.1012:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits -7
+	mov	lr, lr, lsr #1
+	blt	L.4.1008
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #13
+
+		b	9f
+	
+L.4.1008:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #15
+		b	9f
+
+	
+	
+	
+	
+	9:
+Lend_regular_divide:
+	subs	ip, ip, #1
+	bge	Ldivloop
+	cmp	r3, #0
+	@ non-restoring fixup here (one instruction only!)
+	sublt	r2, r2, #1
+
+
+Lgot_result:
+	@ check to see if answer should be < 0
+	cmp	r6, #0
+	rsbmi r2, r2, #0
+
+	mov r0, r2
+	ldmia	sp!, {r4, r5, r6, pc} RETPC
+
+Ldiv_zero:
+	@ Divide by zero trap.  If it returns, return 0 (about as
+	@ wrong as possible, but that is what SunOS does...).
+	bl	___div0
+	mov	r0, #0
+	ldmia	sp!, {r4, r5, r6, pc} RETPC
+
+#endif /* L_divsi3 */
+
+#ifdef L_umodsi3
+
+ip	.req	r12
+sp	.req	r13
+lr	.req	r14
+pc	.req	r15
+.text
+	.globl ___umodsi3
+	.align 0
+___umodsi3:
+	stmdb	sp!, {r4, r5, lr}
+	@ Ready to divide.  Compute size of quotient; scale comparand.
+	movs	lr, r1
+	mov	r3, r0
+	beq	Ldiv_zero
+
+
+	cmp	r3, lr			@ if r1 exceeds r0, done
+	mov	r2, #0
+	bcc	Lgot_result		@ (and algorithm fails otherwise)
+	mov	r4, #(1 << (32 - 4 - 1))
+	cmp	r3, r4
+	mov	ip, #0
+	bcc	Lnot_really_big
+
+	@ Here the dividend is >= 2^(31-N) or so.  We must be careful here,
+	@ as our usual N-at-a-shot divide step will cause overflow and havoc.
+	@ The number of bits in the result here is N*ITER+SC, where SC <= N.
+	@ Compute ITER in an unorthodox manner: know we need to shift V into
+	@ the top decade: so do not even bother to compare to R.
+		mov	r5, #1
+	1:
+		cmp	lr, r4
+		bcs	3f
+		mov	lr, lr, lsl #4
+		add	ip, ip, #1
+		b	1b
+
+	@ Now compute r5.
+	2:	adds	lr, lr, lr
+		add	r5, r5, #1
+		bcc	Lnot_too_big
+
+		@ We get here if the r1 overflowed while shifting.
+		@ This means that r3 has the high-order bit set.
+		@ Restore lr and subtract from r3.
+		mov	r4, r4, lsl #4
+		mov	lr, lr, lsr #1
+		add	lr, r4, lr
+		sub	r5, r5, #1
+		b	Ldo_single_div
+
+	Lnot_too_big:
+	3:	cmp	lr, r3
+		bcc	2b
+@		beq	Ldo_single_div
+
+	/* NB: these are commented out in the V8-Sparc manual as well */
+	/* (I do not understand this) */
+	@ lr > r3: went too far: back up 1 step
+	@	srl	lr, 1, lr
+	@	dec	r5
+	@ do single-bit divide steps
+	@
+	@ We have to be careful here.  We know that r3 >= lr, so we can do the
+	@ first divide step without thinking.  BUT, the others are conditional,
+	@ and are only done if r3 >= 0.  Because both r3 and lr may have the high-
+	@ order bit set in the first step, just falling into the regular
+	@ division loop will mess up the first time around.
+	@ So we unroll slightly...
+	Ldo_single_div:
+		subs	r5, r5, #1
+		blt	Lend_regular_divide
+		sub	r3, r3, lr
+		mov	r2, #1
+		b	Lend_single_divloop
+	Lsingle_divloop:
+		cmp	r3, #0
+		mov	r2, r2, lsl #1
+		mov	lr, lr, lsr #1
+		@ r3 >= 0
+		subpl	r3, r3, lr
+		addpl	r2, r2, #1
+		@ r3 < 0
+		addmi	r3, r3, lr
+		submi	r2, r2, #1
+	Lend_single_divloop:
+		subs	r5, r5, #1
+		bge	Lsingle_divloop
+		b	Lend_regular_divide
+
+1:
+	add	ip, ip, #1
+Lnot_really_big:
+	mov	lr, lr, lsl #4
+	cmp	lr, r3
+	bls	1b
+	@
+	@	HOW CAN ip EVER BE -1 HERE ?????
+	@
+	cmn	ip, #1
+	beq	Lgot_result
+
+Ldivloop:
+	cmp	r3, #0	@ set up for initial iteration
+	mov	r2, r2, lsl #4
+		@ depth 1, accumulated bits 0
+	mov	lr, lr, lsr #1
+	blt	L.1.1015
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 2, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.2.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 3, accumulated bits 3
+	mov	lr, lr, lsr #1
+	blt	L.3.1018
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits 7
+	mov	lr, lr, lsr #1
+	blt	L.4.1022
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #15
+
+		b	9f
+	
+L.4.1022:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #13
+		b	9f
+
+	
+	
+L.3.1018:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits 5
+	mov	lr, lr, lsr #1
+	blt	L.4.1020
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #11
+
+		b	9f
+	
+L.4.1020:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #9
+		b	9f
+
+	
+	
+	
+L.2.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 3, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.3.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits 3
+	mov	lr, lr, lsr #1
+	blt	L.4.1018
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #7
+
+		b	9f
+	
+L.4.1018:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #5
+		b	9f
+
+	
+	
+L.3.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.4.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #3
+
+		b	9f
+	
+L.4.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #1
+		b	9f
+
+	
+	
+	
+	
+L.1.1015:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 2, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.2.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 3, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.3.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.4.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #1
+
+		b	9f
+	
+L.4.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #3
+		b	9f
+
+	
+	
+L.3.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits -3
+	mov	lr, lr, lsr #1
+	blt	L.4.1012
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #5
+
+		b	9f
+	
+L.4.1012:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #7
+		b	9f
+
+	
+	
+	
+L.2.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 3, accumulated bits -3
+	mov	lr, lr, lsr #1
+	blt	L.3.1012
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits -5
+	mov	lr, lr, lsr #1
+	blt	L.4.1010
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #9
+
+		b	9f
+	
+L.4.1010:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #11
+		b	9f
+
+	
+	
+L.3.1012:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits -7
+	mov	lr, lr, lsr #1
+	blt	L.4.1008
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #13
+
+		b	9f
+	
+L.4.1008:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #15
+		b	9f
+
+	
+	
+	
+	
+	9:
+Lend_regular_divide:
+	subs	ip, ip, #1
+	bge	Ldivloop
+	cmp	r3, #0
+	@ non-restoring fixup here (one instruction only!)
+	addlt	r3, r1, r3
+
+
+Lgot_result:
+
+	mov r0, r3
+	ldmia	sp!, {r4, r5, pc} RETPC
+
+Ldiv_zero:
+	@ Divide by zero trap.  If it returns, return 0 (about as
+	@ wrong as possible, but that is what SunOS does...).
+	bl	___div0
+	mov	r0, #0
+	ldmia	sp!, {r4, r5, pc} RETPC
+
+#endif /* L_umodsi3 */
+
+#ifdef L_modsi3
+
+ip	.req	r12
+sp	.req	r13
+lr	.req	r14
+pc	.req	r15
+.text
+	.globl ___modsi3
+	.align 0
+___modsi3:
+	stmdb	sp!, {r4, r5, r6, lr}
+	@ compute sign of result; if neither is negative, no problem
+	mov	r6, r0
+	cmp	r1, #0
+	rsbmi	r1, r1, #0
+	beq	Ldiv_zero
+	mov	lr, r1
+	movs	r3, r0
+	rsbmi	r3, r3, #0	@ make dividend nonnegative
+
+
+	cmp	r3, lr			@ if r1 exceeds r0, done
+	mov	r2, #0
+	bcc	Lgot_result		@ (and algorithm fails otherwise)
+	mov	r4, #(1 << (32 - 4 - 1))
+	cmp	r3, r4
+	mov	ip, #0
+	bcc	Lnot_really_big
+
+	@ Here the dividend is >= 2^(31-N) or so.  We must be careful here,
+	@ as our usual N-at-a-shot divide step will cause overflow and havoc.
+	@ The number of bits in the result here is N*ITER+SC, where SC <= N.
+	@ Compute ITER in an unorthodox manner: know we need to shift V into
+	@ the top decade: so do not even bother to compare to R.
+		mov	r5, #1
+	1:
+		cmp	lr, r4
+		bcs	3f
+		mov	lr, lr, lsl #4
+		add	ip, ip, #1
+		b	1b
+
+	@ Now compute r5.
+	2:	adds	lr, lr, lr
+		add	r5, r5, #1
+		bcc	Lnot_too_big
+
+		@ We get here if the r1 overflowed while shifting.
+		@ This means that r3 has the high-order bit set.
+		@ Restore lr and subtract from r3.
+		mov	r4, r4, lsl #4
+		mov	lr, lr, lsr #1
+		add	lr, r4, lr
+		sub	r5, r5, #1
+		b	Ldo_single_div
+
+	Lnot_too_big:
+	3:	cmp	lr, r3
+		bcc	2b
+@		beq	Ldo_single_div
+
+	/* NB: these are commented out in the V8-Sparc manual as well */
+	/* (I do not understand this) */
+	@ lr > r3: went too far: back up 1 step
+	@	srl	lr, 1, lr
+	@	dec	r5
+	@ do single-bit divide steps
+	@
+	@ We have to be careful here.  We know that r3 >= lr, so we can do the
+	@ first divide step without thinking.  BUT, the others are conditional,
+	@ and are only done if r3 >= 0.  Because both r3 and lr may have the high-
+	@ order bit set in the first step, just falling into the regular
+	@ division loop will mess up the first time around.
+	@ So we unroll slightly...
+	Ldo_single_div:
+		subs	r5, r5, #1
+		blt	Lend_regular_divide
+		sub	r3, r3, lr
+		mov	r2, #1
+		b	Lend_single_divloop
+	Lsingle_divloop:
+		cmp	r3, #0
+		mov	r2, r2, lsl #1
+		mov	lr, lr, lsr #1
+		@ r3 >= 0
+		subpl	r3, r3, lr
+		addpl	r2, r2, #1
+		@ r3 < 0
+		addmi	r3, r3, lr
+		submi	r2, r2, #1
+	Lend_single_divloop:
+		subs	r5, r5, #1
+		bge	Lsingle_divloop
+		b	Lend_regular_divide
+
+1:
+	add	ip, ip, #1
+Lnot_really_big:
+	mov	lr, lr, lsl #4
+	cmp	lr, r3
+	bls	1b
+	@
+	@	HOW CAN ip EVER BE -1 HERE ?????
+	@
+	cmn	ip, #1
+	beq	Lgot_result
+
+Ldivloop:
+	cmp	r3, #0	@ set up for initial iteration
+	mov	r2, r2, lsl #4
+		@ depth 1, accumulated bits 0
+	mov	lr, lr, lsr #1
+	blt	L.1.1015
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 2, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.2.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 3, accumulated bits 3
+	mov	lr, lr, lsr #1
+	blt	L.3.1018
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits 7
+	mov	lr, lr, lsr #1
+	blt	L.4.1022
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #15
+
+		b	9f
+	
+L.4.1022:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #13
+		b	9f
+
+	
+	
+L.3.1018:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits 5
+	mov	lr, lr, lsr #1
+	blt	L.4.1020
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #11
+
+		b	9f
+	
+L.4.1020:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #9
+		b	9f
+
+	
+	
+	
+L.2.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 3, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.3.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits 3
+	mov	lr, lr, lsr #1
+	blt	L.4.1018
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #7
+
+		b	9f
+	
+L.4.1018:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #5
+		b	9f
+
+	
+	
+L.3.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.4.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #3
+
+		b	9f
+	
+L.4.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #1
+		b	9f
+
+	
+	
+	
+	
+L.1.1015:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 2, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.2.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 3, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.3.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.4.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #1
+
+		b	9f
+	
+L.4.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #3
+		b	9f
+
+	
+	
+L.3.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits -3
+	mov	lr, lr, lsr #1
+	blt	L.4.1012
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #5
+
+		b	9f
+	
+L.4.1012:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #7
+		b	9f
+
+	
+	
+	
+L.2.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 3, accumulated bits -3
+	mov	lr, lr, lsr #1
+	blt	L.3.1012
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits -5
+	mov	lr, lr, lsr #1
+	blt	L.4.1010
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #9
+
+		b	9f
+	
+L.4.1010:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #11
+		b	9f
+
+	
+	
+L.3.1012:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits -7
+	mov	lr, lr, lsr #1
+	blt	L.4.1008
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #13
+
+		b	9f
+	
+L.4.1008:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #15
+		b	9f
+
+	
+	
+	
+	
+	9:
+Lend_regular_divide:
+	subs	ip, ip, #1
+	bge	Ldivloop
+	cmp	r3, #0
+	@ non-restoring fixup here (one instruction only!)
+	addlt	r3, r1, r3
+
+
+Lgot_result:
+	@ check to see if answer should be < 0
+	cmp	r6, #0
+	rsbmi r3, r3, #0
+
+	mov r0, r3
+	ldmia	sp!, {r4, r5, r6, pc} RETPC
+
+Ldiv_zero:
+	@ Divide by zero trap.  If it returns, return 0 (about as
+	@ wrong as possible, but that is what SunOS does...).
+	bl	___div0
+	mov	r0, #0
+	ldmia	sp!, {r4, r5, r6, pc} RETPC
+
+#endif /* L_modsi3 */
+
+#ifdef L_dvmd_tls
+
+	.globl ___div0
+	.align 0
+___div0:
+	MOVPC	pc, lr
+
+#endif /* L_divmodsi_tools */
--- /tmp/pp/gcc-2.7.2.2/config/arm/lib1funcs-linuxelf.asm	Wed Jan 28 22:30:30 1998
+++ gcc-2.7.2.2/config/arm/lib1funcs-linuxelf.asm	Sat Jan 17 10:55:20 1998
@@ -0,0 +1,1607 @@
+@ libgcc1 routines for ARM cpu.
+@ Division and remainder, from Appendix E of the Sparc Version 8
+@ Architecture Manual, with fixes from Gordon Irlam.
+@ Rewritten for the ARM by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
+
+/* Copyright (C) 1995 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* As a special exception, if you link this library with other files,
+   some of which are compiled with GCC, to produce an executable,
+   this library does not by itself cause the resulting executable
+   to be covered by the GNU General Public License.
+   This exception does not however invalidate any other reasons why
+   the executable file might be covered by the GNU General Public License.  */
+
+/*
+ * Input: dividend and divisor in r0 and r1 respectively.
+ *
+ * m4 parameters:
+ *  NAME	name of function to generate
+ *  OP		OP=div => r0 / r1; OP=mod => r0 % r1
+ *  S		S=true => signed; S=false => unsigned
+ *
+ * Algorithm parameters:
+ *  N		how many bits per iteration we try to get (4)
+ *  WORDSIZE	total number of bits (32)
+ *
+ * Derived constants:
+ *  TOPBITS	number of bits in the top `decade' of a number
+ *
+ * Important variables:
+ *  Q		the partial quotient under development (initially 0)
+ *  R		the remainder so far, initially the dividend
+ *  ITER	number of main division loop iterations required;
+ *		equal to ceil(log2(quotient) / N).  Note that this
+ *		is the log base (2^N) of the quotient.
+ *  V		the current comparand, initially divisor*2^(ITER*N-1)
+ *
+ * Cost:
+ *  Current estimate for non-large dividend is
+ *	ceil(log2(quotient) / N) * (10 + 7N/2) + C
+ *  A large dividend is one greater than 2^(31-TOPBITS) and takes a
+ *  different path, as the upper bits of the quotient must be developed
+ *  one bit at a time.
+ */
+
+/*
+define(N, `4')dnl
+define(WORDSIZE, `32')dnl
+define(TOPBITS, eval(WORDSIZE - N*((WORDSIZE-1)/N)))dnl
+dnl
+define(dividend, `r0')dnl
+define(divisor, `r1')dnl
+define(Q, `r2')dnl
+define(R, `r3')dnl
+define(ITER, `ip')dnl
+define(V, `lr')dnl
+dnl
+dnl m4 reminder: ifelse(a,b,c,d) => if a is b, then c, else d
+define(T, `r4')dnl
+define(SC, `r5')dnl
+ifelse(S, `true', `define(SIGN, `r6')')dnl
+define(REGLIST, `ifelse(S, `true', `{r4, r5, r6,', `{r4, r5,')')dnl
+define(ret, `ldmia	sp!, REGLIST pc}^')dnl
+dnl
+dnl This is the recursive definition for developing quotient digits.
+dnl
+dnl Parameters:
+dnl  $1	the current depth, 1 <= $1 <= N
+dnl  $2	the current accumulation of quotient bits
+dnl  N	max depth
+dnl
+dnl We add a new bit to $2 and either recurse or insert the bits in
+dnl the quotient.  R, Q, and V are inputs and outputs as defined above;
+dnl the condition codes are expected to reflect the input R, and are
+dnl modified to reflect the output R.
+dnl
+define(DEVELOP_QUOTIENT_BITS,
+`	@ depth $1, accumulated bits $2
+	mov	V, V, lsr #1
+	blt	L.$1.eval(2^N+$2+999)
+	@ remainder is positive
+	subs	R, R, V
+	ifelse($1, N,
+	`	ifelse(eval(2*$2+1<0), `0',
+		`add	Q, Q, `#'eval($2*2+1)',
+		`sub	Q, Q, `#'eval(-($2*2+1))')
+
+		b	9f
+	', `	DEVELOP_QUOTIENT_BITS(incr($1), `eval(2*$2+1)')')
+L.$1.eval(2^N+$2+999):
+	@ remainder is negative
+	adds	R, R, V
+	ifelse($1, N,
+	`	ifelse(eval(2*$2-1<0), `0',
+		`add	Q, Q, `#'eval($2*2-1)',
+		`sub	Q, Q, `#'eval(-($2*2-1))')
+		b	9f
+
+	', `	DEVELOP_QUOTIENT_BITS(incr($1), `eval(2*$2-1)')')
+	ifelse($1, 1, `9:')')dnl
+
+#include "trap.h"
+
+ip	.req	r12
+sp	.req	r13
+lr	.req	r14
+pc	.req	r15
+.text
+	.globl NAME
+	.align 0
+NAME:
+	stmdb	sp!, REGLIST lr}
+ifelse(S, `true',
+`	@ compute sign of result; if neither is negative, no problem
+	ifelse(OP, `div', `eor	SIGN, divisor, dividend	@ compute sign',
+		`mov	SIGN, dividend')
+	cmp	divisor, #0
+	rsbmi	divisor, divisor, #0
+	beq	Ldiv_zero
+	mov	V, divisor
+	movs	R, dividend
+	rsbmi	R, R, #0	@ make dividend nonnegative
+',
+`	@ Ready to divide.  Compute size of quotient; scale comparand.
+	movs	V, divisor
+	mov	R, dividend
+	beq	Ldiv_zero
+')
+
+	cmp	R, V			@ if divisor exceeds dividend, done
+	mov	Q, #0
+	bcc	Lgot_result		@ (and algorithm fails otherwise)
+	mov	T, `#'(1 << (WORDSIZE - TOPBITS - 1))
+	cmp	R, T
+	mov	ITER, #0
+	bcc	Lnot_really_big
+
+	@ `Here the dividend is >= 2^(31-N) or so.  We must be careful here,
+	@ as our usual N-at-a-shot divide step will cause overflow and havoc.
+	@ The number of bits in the result here is N*ITER+SC, where SC <= N.
+	@ Compute ITER in an unorthodox manner: know we need to shift V into
+	@ the top decade: so do not even bother to compare to R.'
+		mov	SC, #1
+	1:
+		cmp	V, T
+		bcs	3f
+		mov	V, V, lsl `#'N
+		add	ITER, ITER, #1
+		b	1b
+
+	@ Now compute SC.
+	2:	adds	V, V, V
+		add	SC, SC, #1
+		bcc	Lnot_too_big
+
+		@ We get here if the divisor overflowed while shifting.
+		@ This means that R has the high-order bit set.
+		@ Restore V and subtract from R.
+		mov	T, T, lsl `#'TOPBITS
+		mov	V, V, lsr #1
+		add	V, T, V
+		sub	SC, SC, #1
+		b	Ldo_single_div
+
+	Lnot_too_big:
+	3:	cmp	V, R
+		bcc	2b
+@		beq	Ldo_single_div
+
+	/-* NB: these are commented out in the V8-Sparc manual as well *-/
+	/-* (I do not understand this) *-/
+	@ V > R: went too far: back up 1 step
+	@	srl	V, 1, V
+	@	dec	SC
+	@ do single-bit divide steps
+	@
+	@ We have to be careful here.  We know that R >= V, so we can do the
+	@ first divide step without thinking.  BUT, the others are conditional,
+	@ and are only done if R >= 0.  Because both R and V may have the high-
+	@ order bit set in the first step, just falling into the regular
+	@ division loop will mess up the first time around.
+	@ So we unroll slightly...
+	Ldo_single_div:
+		subs	SC, SC, #1
+		blt	Lend_regular_divide
+		sub	R, R, V
+		mov	Q, #1
+		b	Lend_single_divloop
+	Lsingle_divloop:
+		cmp	R, #0
+		mov	Q, Q, lsl #1
+		mov	V, V, lsr #1
+		@ R >= 0
+		subpl	R, R, V
+		addpl	Q, Q, #1
+		@ R < 0
+		addmi	R, R, V
+		submi	Q, Q, #1
+	Lend_single_divloop:
+		subs	SC, SC, #1
+		bge	Lsingle_divloop
+		b	Lend_regular_divide
+
+1:
+	add	ITER, ITER, #1
+Lnot_really_big:
+	mov	V, V, lsl `#'N
+	cmp	V, R
+	bls	1b
+	@
+	@	HOW CAN ITER EVER BE -1 HERE ?????
+	@
+	cmn	ITER, #1
+	beq	Lgot_result
+
+Ldivloop:
+	cmp	R, #0	@ set up for initial iteration
+	mov	Q, Q, lsl `#'N
+	DEVELOP_QUOTIENT_BITS(1, 0)
+Lend_regular_divide:
+	subs	ITER, ITER, #1
+	bge	Ldivloop
+	cmp	R, #0
+	@ non-restoring fixup here (one instruction only!)
+ifelse(OP, `div',
+`	sublt	Q, Q, #1
+', `	addlt	R, divisor, R
+')
+
+Lgot_result:
+ifelse(S, `true',
+`	@ check to see if answer should be < 0
+	cmp	SIGN, #0
+	ifelse(OP, `div', `rsbmi Q, Q, #0', `rsbmi R, R, #0')
+')
+	ifelse(OP, `div', `mov r0, Q', `mov r0, R')
+	ret
+
+Ldiv_zero:
+	@ Divide by zero trap.  If it returns, return 0 (about as
+	@ wrong as possible, but that is what SunOS does...).
+	bl	__div0
+	mov	r0, #0
+	ret
+*/
+
+#if defined(__arm6__)
+#define RETPC
+#define MOVPC	mov
+#else
+#define RETPC ^
+#define MOVPC	movs
+#endif
+
+#ifdef Ludivsi3
+
+ip	.req	r12
+sp	.req	r13
+lr	.req	r14
+pc	.req	r15
+.text
+	.globl __udivsi3
+	.align 0
+__udivsi3:
+	stmdb	sp!, {r4, r5, lr}
+	@ Ready to divide.  Compute size of quotient; scale comparand.
+	movs	lr, r1
+	mov	r3, r0
+	beq	Ldiv_zero
+
+
+	cmp	r3, lr			@ if r1 exceeds r0, done
+	mov	r2, #0
+	bcc	Lgot_result		@ (and algorithm fails otherwise)
+	mov	r4, #(1 << (32 - 4 - 1))
+	cmp	r3, r4
+	mov	ip, #0
+	bcc	Lnot_really_big
+
+	@ Here the dividend is >= 2^(31-N) or so.  We must be careful here,
+	@ as our usual N-at-a-shot divide step will cause overflow and havoc.
+	@ The number of bits in the result here is N*ITER+SC, where SC <= N.
+	@ Compute ITER in an unorthodox manner: know we need to shift V into
+	@ the top decade: so do not even bother to compare to R.
+		mov	r5, #1
+	1:
+		cmp	lr, r4
+		bcs	3f
+		mov	lr, lr, lsl #4
+		add	ip, ip, #1
+		b	1b
+
+	@ Now compute r5.
+	2:	adds	lr, lr, lr
+		add	r5, r5, #1
+		bcc	Lnot_too_big
+
+		@ We get here if the r1 overflowed while shifting.
+		@ This means that r3 has the high-order bit set.
+		@ Restore lr and subtract from r3.
+		mov	r4, r4, lsl #4
+		mov	lr, lr, lsr #1
+		add	lr, r4, lr
+		sub	r5, r5, #1
+		b	Ldo_single_div
+
+	Lnot_too_big:
+	3:	cmp	lr, r3
+		bcc	2b
+@		beq	Ldo_single_div
+
+	/* NB: these are commented out in the V8-Sparc manual as well */
+	/* (I do not understand this) */
+	@ lr > r3: went too far: back up 1 step
+	@	srl	lr, 1, lr
+	@	dec	r5
+	@ do single-bit divide steps
+	@
+	@ We have to be careful here.  We know that r3 >= lr, so we can do the
+	@ first divide step without thinking.  BUT, the others are conditional,
+	@ and are only done if r3 >= 0.  Because both r3 and lr may have the high-
+	@ order bit set in the first step, just falling into the regular
+	@ division loop will mess up the first time around.
+	@ So we unroll slightly...
+	Ldo_single_div:
+		subs	r5, r5, #1
+		blt	Lend_regular_divide
+		sub	r3, r3, lr
+		mov	r2, #1
+		b	Lend_single_divloop
+	Lsingle_divloop:
+		cmp	r3, #0
+		mov	r2, r2, lsl #1
+		mov	lr, lr, lsr #1
+		@ r3 >= 0
+		subpl	r3, r3, lr
+		addpl	r2, r2, #1
+		@ r3 < 0
+		addmi	r3, r3, lr
+		submi	r2, r2, #1
+	Lend_single_divloop:
+		subs	r5, r5, #1
+		bge	Lsingle_divloop
+		b	Lend_regular_divide
+
+1:
+	add	ip, ip, #1
+Lnot_really_big:
+	mov	lr, lr, lsl #4
+	cmp	lr, r3
+	bls	1b
+	@
+	@	HOW CAN ip EVER BE -1 HERE ?????
+	@
+	cmn	ip, #1
+	beq	Lgot_result
+
+Ldivloop:
+	cmp	r3, #0	@ set up for initial iteration
+	mov	r2, r2, lsl #4
+		@ depth 1, accumulated bits 0
+	mov	lr, lr, lsr #1
+	blt	L.1.1015
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 2, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.2.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 3, accumulated bits 3
+	mov	lr, lr, lsr #1
+	blt	L.3.1018
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits 7
+	mov	lr, lr, lsr #1
+	blt	L.4.1022
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #15
+
+		b	9f
+	
+L.4.1022:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #13
+		b	9f
+
+	
+	
+L.3.1018:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits 5
+	mov	lr, lr, lsr #1
+	blt	L.4.1020
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #11
+
+		b	9f
+	
+L.4.1020:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #9
+		b	9f
+
+	
+	
+	
+L.2.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 3, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.3.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits 3
+	mov	lr, lr, lsr #1
+	blt	L.4.1018
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #7
+
+		b	9f
+	
+L.4.1018:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #5
+		b	9f
+
+	
+	
+L.3.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.4.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #3
+
+		b	9f
+	
+L.4.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #1
+		b	9f
+
+	
+	
+	
+	
+L.1.1015:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 2, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.2.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 3, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.3.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.4.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #1
+
+		b	9f
+	
+L.4.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #3
+		b	9f
+
+	
+	
+L.3.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits -3
+	mov	lr, lr, lsr #1
+	blt	L.4.1012
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #5
+
+		b	9f
+	
+L.4.1012:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #7
+		b	9f
+
+	
+	
+	
+L.2.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 3, accumulated bits -3
+	mov	lr, lr, lsr #1
+	blt	L.3.1012
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits -5
+	mov	lr, lr, lsr #1
+	blt	L.4.1010
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #9
+
+		b	9f
+	
+L.4.1010:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #11
+		b	9f
+
+	
+	
+L.3.1012:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits -7
+	mov	lr, lr, lsr #1
+	blt	L.4.1008
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #13
+
+		b	9f
+	
+L.4.1008:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #15
+		b	9f
+
+	
+	
+	
+	
+	9:
+Lend_regular_divide:
+	subs	ip, ip, #1
+	bge	Ldivloop
+	cmp	r3, #0
+	@ non-restoring fixup here (one instruction only!)
+	sublt	r2, r2, #1
+
+
+Lgot_result:
+
+	mov r0, r2
+	ldmia	sp!, {r4, r5, pc} RETPC
+
+Ldiv_zero:
+	@ Divide by zero trap.  If it returns, return 0 (about as
+	@ wrong as possible, but that is what SunOS does...).
+	bl	__div0
+	mov	r0, #0
+	ldmia	sp!, {r4, r5, pc} RETPC
+
+#endif /* L_udivsi3 */
+
+#ifdef Ldivsi3
+
+ip	.req	r12
+sp	.req	r13
+lr	.req	r14
+pc	.req	r15
+.text
+	.globl __divsi3
+	.align 0
+__divsi3:
+	stmdb	sp!, {r4, r5, r6, lr}
+	@ compute sign of result; if neither is negative, no problem
+	eor	r6, r1, r0	@ compute sign
+	cmp	r1, #0
+	rsbmi	r1, r1, #0
+	beq	Ldiv_zero
+	mov	lr, r1
+	movs	r3, r0
+	rsbmi	r3, r3, #0	@ make dividend nonnegative
+
+
+	cmp	r3, lr			@ if r1 exceeds r0, done
+	mov	r2, #0
+	bcc	Lgot_result		@ (and algorithm fails otherwise)
+	mov	r4, #(1 << (32 - 4 - 1))
+	cmp	r3, r4
+	mov	ip, #0
+	bcc	Lnot_really_big
+
+	@ Here the dividend is >= 2^(31-N) or so.  We must be careful here,
+	@ as our usual N-at-a-shot divide step will cause overflow and havoc.
+	@ The number of bits in the result here is N*ITER+SC, where SC <= N.
+	@ Compute ITER in an unorthodox manner: know we need to shift V into
+	@ the top decade: so do not even bother to compare to R.
+		mov	r5, #1
+	1:
+		cmp	lr, r4
+		bcs	3f
+		mov	lr, lr, lsl #4
+		add	ip, ip, #1
+		b	1b
+
+	@ Now compute r5.
+	2:	adds	lr, lr, lr
+		add	r5, r5, #1
+		bcc	Lnot_too_big
+
+		@ We get here if the r1 overflowed while shifting.
+		@ This means that r3 has the high-order bit set.
+		@ Restore lr and subtract from r3.
+		mov	r4, r4, lsl #4
+		mov	lr, lr, lsr #1
+		add	lr, r4, lr
+		sub	r5, r5, #1
+		b	Ldo_single_div
+
+	Lnot_too_big:
+	3:	cmp	lr, r3
+		bcc	2b
+@		beq	Ldo_single_div
+
+	/* NB: these are commented out in the V8-Sparc manual as well */
+	/* (I do not understand this) */
+	@ lr > r3: went too far: back up 1 step
+	@	srl	lr, 1, lr
+	@	dec	r5
+	@ do single-bit divide steps
+	@
+	@ We have to be careful here.  We know that r3 >= lr, so we can do the
+	@ first divide step without thinking.  BUT, the others are conditional,
+	@ and are only done if r3 >= 0.  Because both r3 and lr may have the high-
+	@ order bit set in the first step, just falling into the regular
+	@ division loop will mess up the first time around.
+	@ So we unroll slightly...
+	Ldo_single_div:
+		subs	r5, r5, #1
+		blt	Lend_regular_divide
+		sub	r3, r3, lr
+		mov	r2, #1
+		b	Lend_single_divloop
+	Lsingle_divloop:
+		cmp	r3, #0
+		mov	r2, r2, lsl #1
+		mov	lr, lr, lsr #1
+		@ r3 >= 0
+		subpl	r3, r3, lr
+		addpl	r2, r2, #1
+		@ r3 < 0
+		addmi	r3, r3, lr
+		submi	r2, r2, #1
+	Lend_single_divloop:
+		subs	r5, r5, #1
+		bge	Lsingle_divloop
+		b	Lend_regular_divide
+
+1:
+	add	ip, ip, #1
+Lnot_really_big:
+	mov	lr, lr, lsl #4
+	cmp	lr, r3
+	bls	1b
+	@
+	@	HOW CAN ip EVER BE -1 HERE ?????
+	@
+	cmn	ip, #1
+	beq	Lgot_result
+
+Ldivloop:
+	cmp	r3, #0	@ set up for initial iteration
+	mov	r2, r2, lsl #4
+		@ depth 1, accumulated bits 0
+	mov	lr, lr, lsr #1
+	blt	L.1.1015
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 2, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.2.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 3, accumulated bits 3
+	mov	lr, lr, lsr #1
+	blt	L.3.1018
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits 7
+	mov	lr, lr, lsr #1
+	blt	L.4.1022
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #15
+
+		b	9f
+	
+L.4.1022:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #13
+		b	9f
+
+	
+	
+L.3.1018:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits 5
+	mov	lr, lr, lsr #1
+	blt	L.4.1020
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #11
+
+		b	9f
+	
+L.4.1020:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #9
+		b	9f
+
+	
+	
+	
+L.2.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 3, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.3.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits 3
+	mov	lr, lr, lsr #1
+	blt	L.4.1018
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #7
+
+		b	9f
+	
+L.4.1018:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #5
+		b	9f
+
+	
+	
+L.3.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.4.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #3
+
+		b	9f
+	
+L.4.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #1
+		b	9f
+
+	
+	
+	
+	
+L.1.1015:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 2, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.2.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 3, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.3.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.4.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #1
+
+		b	9f
+	
+L.4.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #3
+		b	9f
+
+	
+	
+L.3.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits -3
+	mov	lr, lr, lsr #1
+	blt	L.4.1012
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #5
+
+		b	9f
+	
+L.4.1012:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #7
+		b	9f
+
+	
+	
+	
+L.2.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 3, accumulated bits -3
+	mov	lr, lr, lsr #1
+	blt	L.3.1012
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits -5
+	mov	lr, lr, lsr #1
+	blt	L.4.1010
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #9
+
+		b	9f
+	
+L.4.1010:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #11
+		b	9f
+
+	
+	
+L.3.1012:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits -7
+	mov	lr, lr, lsr #1
+	blt	L.4.1008
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #13
+
+		b	9f
+	
+L.4.1008:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #15
+		b	9f
+
+	
+	
+	
+	
+	9:
+Lend_regular_divide:
+	subs	ip, ip, #1
+	bge	Ldivloop
+	cmp	r3, #0
+	@ non-restoring fixup here (one instruction only!)
+	sublt	r2, r2, #1
+
+
+Lgot_result:
+	@ check to see if answer should be < 0
+	cmp	r6, #0
+	rsbmi r2, r2, #0
+
+	mov r0, r2
+	ldmia	sp!, {r4, r5, r6, pc} RETPC
+
+Ldiv_zero:
+	@ Divide by zero trap.  If it returns, return 0 (about as
+	@ wrong as possible, but that is what SunOS does...).
+	bl	__div0
+	mov	r0, #0
+	ldmia	sp!, {r4, r5, r6, pc} RETPC
+
+#endif /* L_divsi3 */
+
+#ifdef Lumodsi3
+
+ip	.req	r12
+sp	.req	r13
+lr	.req	r14
+pc	.req	r15
+.text
+	.globl __umodsi3
+	.align 0
+__umodsi3:
+	stmdb	sp!, {r4, r5, lr}
+	@ Ready to divide.  Compute size of quotient; scale comparand.
+	movs	lr, r1
+	mov	r3, r0
+	beq	Ldiv_zero
+
+
+	cmp	r3, lr			@ if r1 exceeds r0, done
+	mov	r2, #0
+	bcc	Lgot_result		@ (and algorithm fails otherwise)
+	mov	r4, #(1 << (32 - 4 - 1))
+	cmp	r3, r4
+	mov	ip, #0
+	bcc	Lnot_really_big
+
+	@ Here the dividend is >= 2^(31-N) or so.  We must be careful here,
+	@ as our usual N-at-a-shot divide step will cause overflow and havoc.
+	@ The number of bits in the result here is N*ITER+SC, where SC <= N.
+	@ Compute ITER in an unorthodox manner: know we need to shift V into
+	@ the top decade: so do not even bother to compare to R.
+		mov	r5, #1
+	1:
+		cmp	lr, r4
+		bcs	3f
+		mov	lr, lr, lsl #4
+		add	ip, ip, #1
+		b	1b
+
+	@ Now compute r5.
+	2:	adds	lr, lr, lr
+		add	r5, r5, #1
+		bcc	Lnot_too_big
+
+		@ We get here if the r1 overflowed while shifting.
+		@ This means that r3 has the high-order bit set.
+		@ Restore lr and subtract from r3.
+		mov	r4, r4, lsl #4
+		mov	lr, lr, lsr #1
+		add	lr, r4, lr
+		sub	r5, r5, #1
+		b	Ldo_single_div
+
+	Lnot_too_big:
+	3:	cmp	lr, r3
+		bcc	2b
+@		beq	Ldo_single_div
+
+	/* NB: these are commented out in the V8-Sparc manual as well */
+	/* (I do not understand this) */
+	@ lr > r3: went too far: back up 1 step
+	@	srl	lr, 1, lr
+	@	dec	r5
+	@ do single-bit divide steps
+	@
+	@ We have to be careful here.  We know that r3 >= lr, so we can do the
+	@ first divide step without thinking.  BUT, the others are conditional,
+	@ and are only done if r3 >= 0.  Because both r3 and lr may have the high-
+	@ order bit set in the first step, just falling into the regular
+	@ division loop will mess up the first time around.
+	@ So we unroll slightly...
+	Ldo_single_div:
+		subs	r5, r5, #1
+		blt	Lend_regular_divide
+		sub	r3, r3, lr
+		mov	r2, #1
+		b	Lend_single_divloop
+	Lsingle_divloop:
+		cmp	r3, #0
+		mov	r2, r2, lsl #1
+		mov	lr, lr, lsr #1
+		@ r3 >= 0
+		subpl	r3, r3, lr
+		addpl	r2, r2, #1
+		@ r3 < 0
+		addmi	r3, r3, lr
+		submi	r2, r2, #1
+	Lend_single_divloop:
+		subs	r5, r5, #1
+		bge	Lsingle_divloop
+		b	Lend_regular_divide
+
+1:
+	add	ip, ip, #1
+Lnot_really_big:
+	mov	lr, lr, lsl #4
+	cmp	lr, r3
+	bls	1b
+	@
+	@	HOW CAN ip EVER BE -1 HERE ?????
+	@
+	cmn	ip, #1
+	beq	Lgot_result
+
+Ldivloop:
+	cmp	r3, #0	@ set up for initial iteration
+	mov	r2, r2, lsl #4
+		@ depth 1, accumulated bits 0
+	mov	lr, lr, lsr #1
+	blt	L.1.1015
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 2, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.2.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 3, accumulated bits 3
+	mov	lr, lr, lsr #1
+	blt	L.3.1018
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits 7
+	mov	lr, lr, lsr #1
+	blt	L.4.1022
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #15
+
+		b	9f
+	
+L.4.1022:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #13
+		b	9f
+
+	
+	
+L.3.1018:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits 5
+	mov	lr, lr, lsr #1
+	blt	L.4.1020
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #11
+
+		b	9f
+	
+L.4.1020:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #9
+		b	9f
+
+	
+	
+	
+L.2.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 3, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.3.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits 3
+	mov	lr, lr, lsr #1
+	blt	L.4.1018
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #7
+
+		b	9f
+	
+L.4.1018:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #5
+		b	9f
+
+	
+	
+L.3.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.4.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #3
+
+		b	9f
+	
+L.4.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #1
+		b	9f
+
+	
+	
+	
+	
+L.1.1015:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 2, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.2.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 3, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.3.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.4.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #1
+
+		b	9f
+	
+L.4.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #3
+		b	9f
+
+	
+	
+L.3.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits -3
+	mov	lr, lr, lsr #1
+	blt	L.4.1012
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #5
+
+		b	9f
+	
+L.4.1012:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #7
+		b	9f
+
+	
+	
+	
+L.2.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 3, accumulated bits -3
+	mov	lr, lr, lsr #1
+	blt	L.3.1012
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits -5
+	mov	lr, lr, lsr #1
+	blt	L.4.1010
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #9
+
+		b	9f
+	
+L.4.1010:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #11
+		b	9f
+
+	
+	
+L.3.1012:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits -7
+	mov	lr, lr, lsr #1
+	blt	L.4.1008
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #13
+
+		b	9f
+	
+L.4.1008:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #15
+		b	9f
+
+	
+	
+	
+	
+	9:
+Lend_regular_divide:
+	subs	ip, ip, #1
+	bge	Ldivloop
+	cmp	r3, #0
+	@ non-restoring fixup here (one instruction only!)
+	addlt	r3, r1, r3
+
+
+Lgot_result:
+
+	mov r0, r3
+	ldmia	sp!, {r4, r5, pc} RETPC
+
+Ldiv_zero:
+	@ Divide by zero trap.  If it returns, return 0 (about as
+	@ wrong as possible, but that is what SunOS does...).
+	bl	__div0
+	mov	r0, #0
+	ldmia	sp!, {r4, r5, pc} RETPC
+
+#endif /* L_umodsi3 */
+
+#ifdef Lmodsi3
+
+ip	.req	r12
+sp	.req	r13
+lr	.req	r14
+pc	.req	r15
+.text
+	.globl __modsi3
+	.align 0
+__modsi3:
+	stmdb	sp!, {r4, r5, r6, lr}
+	@ compute sign of result; if neither is negative, no problem
+	mov	r6, r0
+	cmp	r1, #0
+	rsbmi	r1, r1, #0
+	beq	Ldiv_zero
+	mov	lr, r1
+	movs	r3, r0
+	rsbmi	r3, r3, #0	@ make dividend nonnegative
+
+
+	cmp	r3, lr			@ if r1 exceeds r0, done
+	mov	r2, #0
+	bcc	Lgot_result		@ (and algorithm fails otherwise)
+	mov	r4, #(1 << (32 - 4 - 1))
+	cmp	r3, r4
+	mov	ip, #0
+	bcc	Lnot_really_big
+
+	@ Here the dividend is >= 2^(31-N) or so.  We must be careful here,
+	@ as our usual N-at-a-shot divide step will cause overflow and havoc.
+	@ The number of bits in the result here is N*ITER+SC, where SC <= N.
+	@ Compute ITER in an unorthodox manner: know we need to shift V into
+	@ the top decade: so do not even bother to compare to R.
+		mov	r5, #1
+	1:
+		cmp	lr, r4
+		bcs	3f
+		mov	lr, lr, lsl #4
+		add	ip, ip, #1
+		b	1b
+
+	@ Now compute r5.
+	2:	adds	lr, lr, lr
+		add	r5, r5, #1
+		bcc	Lnot_too_big
+
+		@ We get here if the r1 overflowed while shifting.
+		@ This means that r3 has the high-order bit set.
+		@ Restore lr and subtract from r3.
+		mov	r4, r4, lsl #4
+		mov	lr, lr, lsr #1
+		add	lr, r4, lr
+		sub	r5, r5, #1
+		b	Ldo_single_div
+
+	Lnot_too_big:
+	3:	cmp	lr, r3
+		bcc	2b
+@		beq	Ldo_single_div
+
+	/* NB: these are commented out in the V8-Sparc manual as well */
+	/* (I do not understand this) */
+	@ lr > r3: went too far: back up 1 step
+	@	srl	lr, 1, lr
+	@	dec	r5
+	@ do single-bit divide steps
+	@
+	@ We have to be careful here.  We know that r3 >= lr, so we can do the
+	@ first divide step without thinking.  BUT, the others are conditional,
+	@ and are only done if r3 >= 0.  Because both r3 and lr may have the high-
+	@ order bit set in the first step, just falling into the regular
+	@ division loop will mess up the first time around.
+	@ So we unroll slightly...
+	Ldo_single_div:
+		subs	r5, r5, #1
+		blt	Lend_regular_divide
+		sub	r3, r3, lr
+		mov	r2, #1
+		b	Lend_single_divloop
+	Lsingle_divloop:
+		cmp	r3, #0
+		mov	r2, r2, lsl #1
+		mov	lr, lr, lsr #1
+		@ r3 >= 0
+		subpl	r3, r3, lr
+		addpl	r2, r2, #1
+		@ r3 < 0
+		addmi	r3, r3, lr
+		submi	r2, r2, #1
+	Lend_single_divloop:
+		subs	r5, r5, #1
+		bge	Lsingle_divloop
+		b	Lend_regular_divide
+
+1:
+	add	ip, ip, #1
+Lnot_really_big:
+	mov	lr, lr, lsl #4
+	cmp	lr, r3
+	bls	1b
+	@
+	@	HOW CAN ip EVER BE -1 HERE ?????
+	@
+	cmn	ip, #1
+	beq	Lgot_result
+
+Ldivloop:
+	cmp	r3, #0	@ set up for initial iteration
+	mov	r2, r2, lsl #4
+		@ depth 1, accumulated bits 0
+	mov	lr, lr, lsr #1
+	blt	L.1.1015
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 2, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.2.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 3, accumulated bits 3
+	mov	lr, lr, lsr #1
+	blt	L.3.1018
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits 7
+	mov	lr, lr, lsr #1
+	blt	L.4.1022
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #15
+
+		b	9f
+	
+L.4.1022:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #13
+		b	9f
+
+	
+	
+L.3.1018:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits 5
+	mov	lr, lr, lsr #1
+	blt	L.4.1020
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #11
+
+		b	9f
+	
+L.4.1020:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #9
+		b	9f
+
+	
+	
+	
+L.2.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 3, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.3.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits 3
+	mov	lr, lr, lsr #1
+	blt	L.4.1018
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #7
+
+		b	9f
+	
+L.4.1018:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #5
+		b	9f
+
+	
+	
+L.3.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits 1
+	mov	lr, lr, lsr #1
+	blt	L.4.1016
+	@ remainder is positive
+	subs	r3, r3, lr
+		add	r2, r2, #3
+
+		b	9f
+	
+L.4.1016:
+	@ remainder is negative
+	adds	r3, r3, lr
+		add	r2, r2, #1
+		b	9f
+
+	
+	
+	
+	
+L.1.1015:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 2, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.2.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 3, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.3.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits -1
+	mov	lr, lr, lsr #1
+	blt	L.4.1014
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #1
+
+		b	9f
+	
+L.4.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #3
+		b	9f
+
+	
+	
+L.3.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits -3
+	mov	lr, lr, lsr #1
+	blt	L.4.1012
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #5
+
+		b	9f
+	
+L.4.1012:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #7
+		b	9f
+
+	
+	
+	
+L.2.1014:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 3, accumulated bits -3
+	mov	lr, lr, lsr #1
+	blt	L.3.1012
+	@ remainder is positive
+	subs	r3, r3, lr
+			@ depth 4, accumulated bits -5
+	mov	lr, lr, lsr #1
+	blt	L.4.1010
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #9
+
+		b	9f
+	
+L.4.1010:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #11
+		b	9f
+
+	
+	
+L.3.1012:
+	@ remainder is negative
+	adds	r3, r3, lr
+			@ depth 4, accumulated bits -7
+	mov	lr, lr, lsr #1
+	blt	L.4.1008
+	@ remainder is positive
+	subs	r3, r3, lr
+		sub	r2, r2, #13
+
+		b	9f
+	
+L.4.1008:
+	@ remainder is negative
+	adds	r3, r3, lr
+		sub	r2, r2, #15
+		b	9f
+
+	
+	
+	
+	
+	9:
+Lend_regular_divide:
+	subs	ip, ip, #1
+	bge	Ldivloop
+	cmp	r3, #0
+	@ non-restoring fixup here (one instruction only!)
+	addlt	r3, r1, r3
+
+
+Lgot_result:
+	@ check to see if answer should be < 0
+	cmp	r6, #0
+	rsbmi r3, r3, #0
+
+	mov r0, r3
+	ldmia	sp!, {r4, r5, r6, pc} RETPC
+
+Ldiv_zero:
+	@ Divide by zero trap.  If it returns, return 0 (about as
+	@ wrong as possible, but that is what SunOS does...).
+	bl	__div0
+	mov	r0, #0
+	ldmia	sp!, {r4, r5, r6, pc} RETPC
+
+#endif /* L_modsi3 */
+
+#ifdef Ldvmd_tls
+
+	.globl __div0
+	.align 0
+__div0:
+	MOVPC	pc, lr
+
+#endif /* L_divmodsi_tools */
--- /tmp/pp/gcc-2.7.2.2/config/arm/linux-aout.h	Wed Jan 28 22:30:30 1998
+++ gcc-2.7.2.2/config/arm/linux-aout.h	Sat Nov 29 15:42:38 1997
@@ -0,0 +1,89 @@
+/* Definitions for ARM running Linux with A.OUT format
+   Copyright (C) 1993, 1994 Free Software Foundation, Inc.
+   Origional:
+   Contributed by Richard Earnshaw (rwe11@cl.cam.ac.uk), based on original
+	      work by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
+   	      and Martin Simmons (@harleqn.co.uk).
+   Adapted to ARM Linux/aout by R.M.King
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#include <linux-aout.h> /* some common stuff */
+
+/* Specify predefined symbols in preprocessor.  */
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES \
+	"-Dunix -Darm -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(arm) -Amachine(arm)"
+
+#undef CPP_SPEC
+#define CPP_SPEC \
+	"%{m2:-D__arm2__} %{m3:-D__arm3__} %{m6:-D__arm6__} %{m7:-D__arm7__} " \
+	"%{!m2:%{!m3:%{!m6:%{!m7:" __DEFAULT_CPP "}}}} %{posix:-D_POSIX_SOURCE}"
+
+#undef SIZE_TYPE
+#define SIZE_TYPE "unsigned int"
+
+#undef PTRDIFF_TYPE
+#define PTRDIFF_TYPE "int"
+
+#undef WCHAR_TYPE
+#define WCHAR_TYPE "long int"
+
+#undef WCHAR_TYPE_SIZE
+#define WCHAR_TYPE_SIZE BITS_PER_WORD
+
+#undef LIB_SPEC
+#define LIB_SPEC \
+	"%{mieee-fp:-lieee} %{p:-lgmon} %{pg:-lgmon} %{!ggdb:-lc} %{ggdb:-lg}"
+
+#undef ASM_APP_ON
+#define ASM_APP_ON	"@APP\n"
+
+#undef ASM_APP_OFF
+#define ASM_APP_OFF	"@NO_APP\n"
+
+#undef COMMENT_BEGIN
+#define COMMENT_BEGIN	"@"
+
+/*
+ * we default to ARM3
+ */
+#define __DEFAULT_CPP "-D__arm3__"
+#define __DEFAULT_ASM "-marm3"
+#define __DEFAULT_MLB "m3"
+
+#undef ASM_SPEC
+#define ASM_SPEC \
+	"%{m2:-marm2} %{m3:-marm3} %{m6:-marm6} %{m7:-marm7} " \
+	"%{!m2:%{!m3:%{!m6:%{!m7:" __DEFAULT_ASM "}}}}"
+
+#define TARGET_VERSION  fputs (" (ARM Linux/a.out)", stderr);
+#define NO_REQ
+
+/* This is used in ASM_FILE_START */
+#define ARM_OS_NAME "Linux"
+
+/* Unsigned chars produces much better code than signed.  */
+#define DEFAULT_SIGNED_CHAR 0
+
+/* Maths operation domain error number, EDOM */
+#define TARGET_EDOM 33
+#include "arm/arm.h"
+
+#undef MULTILIB_DEFAULTS
+#define MULTILIB_DEFAULTS { __DEFAULT_MLB }
--- /tmp/pp/gcc-2.7.2.2/config/arm/linux-elf.h	Wed Jan 28 22:30:30 1998
+++ gcc-2.7.2.2/config/arm/linux-elf.h	Sun Jan 25 11:47:45 1998
@@ -0,0 +1,163 @@
+/* Definitions for ARM running Linux with ELF format
+   Copyright (C) 1993, 1994 Free Software Foundation, Inc.
+   Origional:
+   Contributed by Richard Earnshaw (rwe11@cl.cam.ac.uk), based on original
+	      work by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
+   	      and Martin Simmons (@harleqn.co.uk).
+   Adapted to ARM Linux/aout by R.M.King
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#include <linux.h> /* some common stuff */
+
+#define SUPPORT_PIC
+
+/* Specify predefined symbols in preprocessor.  */
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES \
+	"-D__ELF__ -Dunix -Darm -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(arm) -Amachine(arm)"
+
+#undef CPP_SPEC
+#define CPP_SPEC \
+	"%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} " \
+	"%{m2:-D__arm2__} %{m3:-D__arm3__} %{m6:-D__arm6__} %{m7:-D__arm7__} " \
+	"%{!m2:%{!m3:%{!m6:%{!m7:" __DEFAULT_CPP "}}}} %{posix:-D_POSIX_SOURCE}"
+
+#undef  SIZE_TYPE
+#define SIZE_TYPE "unsigned int"
+
+#undef  PTRDIFF_TYPE
+#define PTRDIFF_TYPE "int"
+
+#undef  WCHAR_TYPE
+#define WCHAR_TYPE "long int"
+
+#undef  WCHAR_TYPE_SIZE
+#define WCHAR_TYPE_SIZE BITS_PER_WORD
+
+#undef  LIB_SPEC
+#define LIB_SPEC \
+	"%{!shared: %{mieee-fp:-lieee} %{p:-lgmon} %{pg:-lgmon} %{!ggdb:-lc} %{ggdb:-lg}}"
+
+#undef  LINK_SPEC
+#define LINK_SPEC "-m elf_arm %{shared:-shared} " \
+	"%{!shared: "\
+	  "%{!static: "\
+	    "%{rdynamic:-export-dynamic} "\
+	    "%{!dynamic-linker:-dynamic-linker /lib/ld-linux.so.1}} " \
+	  "%{static:-static}}"
+
+#undef ASM_APP_ON
+#define ASM_APP_ON	"@APP\n"
+
+#undef ASM_APP_OFF
+#define ASM_APP_OFF	"@NO_APP\n"
+
+#undef COMMENT_BEGIN
+#define COMMENT_BEGIN	"@"
+
+/*
+ * we default to ARM6
+ */
+#define __DEFAULT_CPP "-D__arm6__"
+#define __DEFAULT_ASM "-marm6"
+#define __DEFAULT_MLB "m6"
+
+#define TARGET_DEFAULT 8
+
+#undef ASM_SPEC
+#define ASM_SPEC \
+	"%{m2:-marm2} %{m3:-marm3} %{m6:-marm6} %{m7:-marm7} " \
+	"%{!m2:%{!m3:%{!m6:%{!m7:" __DEFAULT_ASM "}}}}"
+
+#define TARGET_VERSION  fputs (" (ARM Linux/ELF)", stderr);
+#define NO_REQ
+
+/* Unsigned chars produces much better code than signed.  */
+#define DEFAULT_SIGNED_CHAR 0
+
+#undef TYPE_OPERAND_FMT
+#define TYPE_OPERAND_FMT	"#%s"
+
+/* Maths operation domain error number, EDOM */
+#define TARGET_EDOM 33
+
+#undef ASM_OUTPUT_ASCII
+#undef ASM_OUTPUT_SKIP
+#undef DWARF_DEBUGGING_INFO
+#undef USE_CONST_SECTION
+#define USE_CONST_SECTION 0
+
+#undef ASM_OUTPUT_INTERNAL_LABEL
+
+#include "arm/arm.h"
+
+#undef MULTILIB_DEFAULTS
+#define MULTILIB_DEFAULTS { __DEFAULT_MLB }
+
+#undef CONSTANT_ALIGNMENT
+#undef INTERNAL_LABEL_FORMAT
+#define INTERNAL_LABEL_FORMAT	".%s%d"
+
+#undef ASM_OUTPUT_INT
+extern void output_pic_addr_const ();
+#define ASM_OUTPUT_INT(STREAM, EXP)				\
+  do {								\
+    fprintf (STREAM, "\t.word\t");				\
+    if (flag_pic)						\
+      output_pic_addr_const (STREAM, (EXP));			\
+    else							\
+      output_addr_const (STREAM, (EXP));			\
+    arm_increase_location (4);					\
+    fputc ('\n', STREAM);					\
+  } while (0)
+
+/*
+ * Argh! ARM uses SYMBOL_REF_FLAG for other purposes!
+ */
+#undef ENCODE_SECTION_INFO
+#define ENCODE_SECTION_INFO(DECL)					\
+  do {									\
+    rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd'		\
+               ? TREE_CST_RTL (DECL) : DECL_RTL (DECL));		\
+    if (flag_pic)							\
+      {									\
+        (XEXP (rtl, 0)->in_struct) =					\
+            (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd'			\
+             || !TREE_PUBLIC (DECL));					\
+      }									\
+    if (optimize > 0 && TREE_CONSTANT (DECL)				\
+        && (!flag_writable_strings || TREE_CODE (DECL) != STRING_CST))	\
+      {									\
+        SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;				\
+      }									\
+  } while (0)
+
+/*
+ * We must make sure that the constant pool is in the same section
+ * As the function that uses it, or else things'll go wrong!
+ */
+#define ASM_OUTPUT_POOL_PROLOGUE(FILE, NAME, DECL, POOL)	\
+	function_section (DECL)
+
+/*
+ * We rely on the above definition to select the correct
+ * section for the constant pool
+ */
+#undef SELECT_RTX_SECTION
+#define SELECT_RTX_SECTION(MODE,RTX)
--- /tmp/pp/gcc-2.7.2.2/config/arm/linux-gas.h	Wed Jan 28 22:30:30 1998
+++ gcc-2.7.2.2/config/arm/linux-gas.h	Sun Jul 21 18:53:05 1996
@@ -0,0 +1,42 @@
+/* Definitions of target machine for GNU compiler.  ARM RISCiX(stabs) version.
+   Copyright (C) 1993 Free Software Foundation, Inc.
+   Contributed by Richard Earnshaw (rwe11@cl.cam.ac.uk), based on original
+	      work by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
+   	      and Martin Simmons (@harleqn.co.uk).
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+/* Limit the length of a stabs entry (for the broken Acorn assembler) */
+#define DBX_CONTIN_LENGTH 80
+
+#include "arm/linux.h"
+
+/*
+ * We are using GAS, so stabs should work.
+ */
+
+#ifndef DBX_DEBUGGING_INFO
+#define DBX_DEBUGGING_INFO 1
+#endif
+
+/* Unfortunately dbx doesn't understand these */
+/* Dbx on RISCiX is so broken that I've given up trying to support it.
+   lets just support gdb. */
+/* #define DEFAULT_GDB_EXTENSIONS 0 */
+/* RISCiX dbx doesn't accept xrefs */
+/* #define DBX_NO_XREFS 1 */
+
--- /tmp/pp/gcc-2.7.2.2/config/arm/linux.h	Wed Jan 28 22:30:30 1998
+++ gcc-2.7.2.2/config/arm/linux.h	Fri Nov 28 18:06:44 1997
@@ -0,0 +1,97 @@
+/* Definitions for ARM running Linux
+   Copyright (C) 1993, 1994 Free Software Foundation, Inc.
+   Origional:
+   Contributed by Richard Earnshaw (rwe11@cl.cam.ac.uk), based on original
+	      work by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
+   	      and Martin Simmons (@harleqn.co.uk).
+   Adapted from ARM Linux by R.M.King
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#include <linux-aout.h> /* some common stuff */
+
+/* these are different... */
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC \
+	"%{pg:gcrt0.o%s} %{!pg:%{p:gcrt0.o%s} %{!p:crt0.o%s}} %{static:-static}"
+
+#undef ASM_APP_ON
+#undef ASM_APP_OFF
+#undef COMMENT_BEGIN
+/*
+ * we default to ARM3
+ */
+#define __DEFAULT_CPP "-D__arm6__"
+#define __DEFAULT_ASM "-marm6"
+#define __DEFAULT_MLB "m6"
+
+/* Specify predefined symbols in preprocessor.  */
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES \
+	"-Dunix -Darm -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(arm) -Amachine(arm)"
+
+#undef CPP_SPEC
+#define CPP_SPEC \
+	"%{m2:-D__arm2__} %{m3:-D__arm3__} %{m6:-D__arm6__} %{m7:-D__arm7__} " \
+	"%{!m2:%{!m3:%{!m6:%{!m7:" __DEFAULT_CPP "}}}} %{posix:-D_POSIX_SOURCE}"
+
+#undef ASM_SPEC
+#define ASM_SPEC \
+	"%{m2:-marm2} %{m3:-marm3} %{m6:-marm6} %{m7:-marm7} " \
+	"%{!m2:%{!m3:%{!m6:%{!m7:" __DEFAULT_ASM "}}}}"
+
+#undef LIB_SPEC
+#define LIB_SPEC \
+	"%{mieee-fp:-lieee} %{p:-lgmon} %{pg:-lgmon} %{!ggdb:-lc} %{ggdb:-lg}"
+
+#undef SIZE_TYPE
+#define SIZE_TYPE "unsigned int"
+
+#undef PTRDIFF_TYPE
+#define PTRDIFF_TYPE "int"
+
+#undef WCHAR_TYPE
+#define WCHAR_TYPE "long int"
+
+#undef WCHAR_TYPE_SIZE
+#define WCHAR_TYPE_SIZE BITS_PER_WORD
+
+#define HANDLE_SYSV_PRAGMA
+  
+/* Run-time Target Specification.  */
+#ifdef GCC_AOUT
+#define TARGET_VERSION  fputs (" (ARM Linux/a.out)", stderr);
+#else
+#define TARGET_VERSION  fputs (" (ARM Linux/ELF)", stderr);
+#define NO_UNDERSCORES
+#endif
+
+#define NO_REQ
+
+/* This is used in ASM_FILE_START */
+#define ARM_OS_NAME "Linux"
+
+/* Unsigned chars produces much better code than signed.  */
+#define DEFAULT_SIGNED_CHAR 0
+
+/* Maths operation domain error number, EDOM */
+#define TARGET_EDOM 33
+#include "arm/arm.h"
+
+#undef MULTILIB_DEFAULTS
+#define MULTILIB_DEFAULTS { __DEFAULT_MLB }
--- /tmp/pp/gcc-2.7.2.2/config/arm/t-linux	Wed Jan 28 22:30:30 1998
+++ gcc-2.7.2.2/config/arm/t-linux	Sat Jun 28 21:29:45 1997
@@ -0,0 +1,17 @@
+# Just for these, we omit the frame pointer since it makes such a big
+# difference.  It is then pointless adding debugging.
+LIBGCC2_CFLAGS=-O2 -fomit-frame-pointer $(LIBGCC2_INCLUDES) $(GCC_CFLAGS) -g0
+
+# Don't build enquire
+ENQUIRE=
+
+CROSS_LIBGCC1 = libgcc1-asm.a
+LIBGCC1 = libgcc1-asm.a
+LIB1ASMSRC = arm/lib1funcs-linux.asm
+LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls
+
+MULTILIB_OPTIONS = m2/m3/m6
+MULTILIB_DIRNAMES =
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
--- /tmp/pp/gcc-2.7.2.2/config/arm/t-linuxelf	Wed Jan 28 22:30:30 1998
+++ gcc-2.7.2.2/config/arm/t-linuxelf	Sat Jan 17 10:48:32 1998
@@ -0,0 +1,18 @@
+# Just for these, we omit the frame pointer since it makes such a big
+# difference.  It is then pointless adding debugging.
+LIBGCC2_CFLAGS=-O2 -fomit-frame-pointer $(LIBGCC2_INCLUDES) $(GCC_CFLAGS) -g0 -I/usr/include
+
+# Don't build enquire
+ENQUIRE=
+
+CROSS_LIBGCC1 = libgcc1-asm.a
+LIBGCC1 = libgcc1-asm.a
+LIB1ASMSRC = arm/lib1funcs-linuxelf.asm
+LIB1ASMFUNCS = udivsi3 divsi3 umodsi3 modsi3 dvmd_tls
+
+MULTILIB_OPTIONS = m2/m3/m6
+MULTILIB_DIRNAMES =
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
+
--- /tmp/pp/gcc-2.7.2.2/config/arm/xm-linux.h	Wed Jan 28 22:30:30 1998
+++ gcc-2.7.2.2/config/arm/xm-linux.h	Sun Jul 21 18:53:05 1996
@@ -0,0 +1,24 @@
+/* Configuration for GCC for Intel i386 running Linux.
+   Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc.
+   Contributed by H.J. Lu (hjl@nynexst.com)
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#include <arm/xm-arm.h>
+#include <xm-linux.h>
+
--- /tmp/pp/gcc-2.7.2.2/config/xm-linux.h	Thu Jun 15 13:54:34 1995
+++ gcc-2.7.2.2/config/xm-linux.h	Sun Jul 21 18:53:06 1996
@@ -19,12 +19,16 @@
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
+#undef  HAVE_VPRINTF
 #define HAVE_VPRINTF
 
+#undef  HAVE_STRERROR
 #define HAVE_STRERROR
 
+#undef  POSIX
 #define POSIX
 
+#undef  DONT_DECLARE_SYS_SIGLIST
 #define DONT_DECLARE_SYS_SIGLIST
 
 /* We do have one, but I'd like to use the one come with gcc since
--- /tmp/pp/gcc-2.7.2.2/configure	Thu Jan 30 22:20:15 1997
+++ gcc-2.7.2.2/configure	Fri Jan 16 23:40:13 1998
@@ -619,6 +619,26 @@
 		tmake_file=arm/t-semi
 		fixincludes=Makefile.in # There is nothing to fix
 		;;
+	arm-*-linux*aout*)		# ARM Linux (aout)
+		cpu_type=arm
+		xm_file=arm/xm-linux.h
+		xmake_file=x-linux
+		tm_file=arm/linux-aout.h
+		tmake_file=arm/t-linux
+		fixincludes=Makefile.in
+		broken_install=yes
+		gnu_ld=yes
+		;;
+	arm-*-linux*)			# ARM Linux (ELF)
+		cpu_type=arm
+		xm_file=arm/xm-linux.h
+		xmake_file=x-linux
+		tm_file=arm/linux-elf.h
+		tmake_file=arm/t-linuxelf
+		fixincludes=Makefile.in
+		broken_install=yes
+		gnu_ld=yes
+		;;
 	arm-*-*)			# generic version
 		;;
 	c1-convex-*)			# Convex C1
