Subject: Changing SA-1100 clock frequency

From: Mark Huang <[email-masked]>
Date: Thu, 16 Sep 1999 16:23:48 EDT

Hi,

Is there a way to update the SA-1100's PPCR register and change the core
clock frequency on the fly after booting Linux? I've tried running the
assembly code that I use to set the core clock before booting, but that
just hangs the system usually. 

Thanks in advance,

--Mark
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From: Nicolas Pitre <[email-masked]>
Date: Thu, 16 Sep 1999 20:12:51 -0400 (EDT)

> just hangs the system usually. 

Why would you do that?  The problem is that most configurable timings like
dram, IO bus, etc. are all configured relative to the core clock.  By
changing the clock you may lose your dram refresh rate and then anything
funny can happen.

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From: Deborah Wallach <[email-masked]>
Date: Thu, 16 Sep 1999 20:52:24 -0400 (EDT)

One reason to do it would potentially be for power savings.  We do it, so
it definitely is possible.  The strategy that we use is to basically shut
down all the devices, jump to a very tiny piece of code in flash that
changes the dram configuration parameters, then change the ppcr and then
start up all the devices again.  There's some funkiness about the order you
do things in depending on whether you're decreasing or increasing the clock
rate, too.

			-Debby

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From: Ben Williamson <[email-masked]>
Date: Thu, 16 Sep 1999 19:57:26 -0700 (PDT)

> just hangs the system usually. 

This is not something you would want to do too often, as that register
controls the PLL that drives the clocks.  When you change the register,
I believe the clock is gated off for a while to give the PLL time to
settle into the new rate.  That means that all peripherals are dead for a
while too.  But I can see how you might get a power saving if you can find
the appropriate moment to do it.

BTW, I think parts like the EP7211 will have a register that varies the
clock rate over a much smaller set of values, by switching divider values.
That avoids the clock while the PLL settles, so it's more useful for power
saving without interrupting peripherals.

Cheers,

- Ben.

-------------------------------------------------------------------
Ben Williamson       [email-masked]     http://www.pobox.com/~benw/

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From: Nicolas Pitre <[email-masked]>
Date: Fri, 17 Sep 1999 11:20:05 -0400 (EDT)

> do things in depending on whether you're decreasing or increasing the clock

Is it really worth the trouble since the wait-on-irq mode can be used when
there's nothing left to do?  Having a hier clock rate will just lead the
CPU faster in the idle mode and stay longer idle.  Power saving should be
about the same in both cases.

Nicolas

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From: Ben Williamson <[email-masked]>
Date: Fri, 17 Sep 1999 11:58:34 -0700 (PDT)

> about the same in both cases.

In terms of power consumption of the core itself, that's certainly true.
But real miserly folks like to worry about the current draw of the PLL and
peripheral circuits that aren't affected by idle mode.  I wonder, Deborah,
do you have any figures?

Cheers,

- Ben.

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From: Deborah Wallach <[email-masked]>
Date: Mon, 20 Sep 1999 18:49:39 -0700 (PDT)

It may not be exactly the same for all cases.  We're in the process of
investigating that right now.   

			-Debby