Subject: LDM & STM

From: "Adam 'WeirdArms' Wiggins" <[email-masked]>
Date: Wed, 15 Sep 1999 01:05:57 +1000 (EST)

Would the following instruction use the user_sp or the svc_sp as
the base register if run in svc mode:

        stmdb   sp, {sp, lr}^                   @ Stack usr_sp, usr_lr

likewise for the ldmia companion. The ARM ARM seems a little vague on the
issue.

	All help apreciated, Adam

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From: Philip Blundell <[email-masked]>
Date: Tue, 14 Sep 1999 17:19:13 +0100

>        stmdb   sp, {sp, lr}^                   @ Stack usr_sp, usr_lr

The architecture may leave it undefined.  Back in days of yore (ARM2 and so 
on) I am fairly sure it took the base from the current register bank, ie SVC.  
If you asked for writeback then the base would be read from the SVC bank but 
written back to the USR one which is probably not what you'd want.

p.

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From: "Adam 'WeirdArms' Wiggins" <[email-masked]>
Date: Wed, 15 Sep 1999 02:25:17 +1000 (EST)

> written back to the USR one which is probably not what you'd want.

	Don't care about write back (not using it in this case). I'm
interested in gerneral ARM3/4. In particular StrongARM but I have a
PS7110 (Psion 5) unit too. What do these chips do? 

	Cheers Adam

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From: "Adam 'WeirdArms' Wiggins" <[email-masked]>
Date: Wed, 15 Sep 1999 04:08:26 +1000 (EST)

> written back to the USR one which is probably not what you'd want.

	Oops, reading the fine print. The Base register is taken from the
current mode. Writeback is implimentation defined. 

	Cheers Adam

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From: [email-masked]
Date: Tue, 14 Sep 1999 19:40:15 +0100 (BST)

> PS7110 (Psion 5) unit too. What do these chips do? 

I would recommend against this instruction.  There has already been one
bug in the StrongARM related to user-mode STMs from SVC.  I think that
the general advice given at that time was not to use any banked register
with a user-mode stm.
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From: "Adam 'WeirdArms' Wiggins" <[email-masked]>
Date: Wed, 15 Sep 1999 22:32:56 +1000 (EST)

> the general advice given at that time was not to use any banked register

	If this is the one concerning page faults during a stm then its
not relavent (kernel stacks in this case never cross page bounds). If its
something else please forward the details to me.

	Many thanks, Adam

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From: [email-masked]
Date: Wed, 15 Sep 1999 20:49:42 +0100 (BST)

> something else please forward the details to me.

No, it's not.  It's the bug where the stack gets messed up by having an
extra word inserted into it.  I don't think Intel published it, but it
was well known by both Acorn and DEC (and DEC used to acknowledge its
existance).
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From: "Adam 'WeirdArms' Wiggins" <[email-masked]>
Date: Thu, 16 Sep 1999 20:09:39 +1000 (EST)

> was well known by both Acorn and DEC (and DEC used to acknowledge its

	Where does the extra word get inserted? Depending on the behaviour
it might not interfere with what I'm using it for. DO you have a reference
for more info on this?

	Cheers Adam

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From: [email-masked]
Date: Thu, 16 Sep 1999 20:33:52 +0100 (BST)

> it might not interfere with what I'm using it for. DO you have a reference

I think it's between the top word and the second one down (top being highest
address value).  However, I can't really remember, it was discovered around
4 years ago while I was porting to the EBSA-110.  I haven't recently seen it
documented anywhere.
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From: "Adam 'WeirdArms' Wiggins" <[email-masked]>
Date: Fri, 17 Sep 1999 19:01:12 +1000 (EST)

> 4 years ago while I was porting to the EBSA-110.  I haven't recently seen it

	Thanks, I'll keep an eye out for it. Maybe they fixed the silicon
since then?

	Cheers Adam

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From: [email-masked]
Date: Fri, 17 Sep 1999 20:35:14 +0100 (BST)

> 	Thanks, I'll keep an eye out for it. Maybe they fixed the silicon

The info I got from DEC after reporting the bug to them (and having it
confirmed) was that they did not see the point in correcting the bug;
they instead issued a work around for it.

However, I may be mistaken - it was 4 years ago.
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