Subject: Problem with 285 and Am79C973

From: Benjamin Herrenschmidt <[email-masked]>
Date: Mon, 19 Jul 1999 11:18:15 +0200

Hi !

I'm working on a driver for the Am79C973 Ethernet controller that we use
on our board. (The Linux PCNet driver needs to be adapted a little bit
for ARM and for this chip, but I'm beginning with a driver for Russel's BIOS).

I'm having a problem with both our board and the EBSA285 with the AMD
evaluation board (so it doesn't look like a HW problem).

Basically, what happens is that apparently, the Ethernet chip incorrectly
reads datas from memory. For example, the initialisation block seems to
be read ok (eth address is correct) except for the _last_ long word (the
Tx ring address): the chip seems to read twice the Rx ring address.
(After initialisation, when I read both ring base addresses via CSR
registers, it looks like the chip used the same address for both Rx and
Tx ring).

Also, ethernet frames sent by the controller seems to be partially
garbled. For ex, if the packet begins with 10 10 10 10 10 10 (hex source
address), on another machine using iptraf, I see those packets coming
with an address of 10 10 ff ff 10 10.

Any clue about what's going on ? I think I have tried almost all possible
configuration options of this ethernet chip, is it possible that there is
some incompatibility between this chip and the 285 ?

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From: Benjamin Herrenschmidt <[email-masked]>
Date: Mon, 19 Jul 1999 12:42:02 +0200

>some incompatibility between this chip and the 285 ?

Note that this is not a cache coherency problem, the bios runs with cache
off. I did add some cache flush/inval. code in case I want to turn the
cache on in a future version. Note that the linux pcnet driver needs to
be adapted for cache incoherency, but this is another matter and
apparently not the source of my problem.