Subject: MMU bug in Dec/Intel ARMs?

From: "Stephen Noftall" <[email-masked]>
Date: Thu, 11 Mar 1999 09:46:34 -0700

I just heard from Intel that they are coming out with a new SA-110, that
supposedly fixes a bug only found in demand paged memory management OS's. The
new part numbers are 21281-xB.

Has anyone heard more on this? Does the MMU unit work around this "bug" or was
the field ap person mis-informed?

{- Stephen Noftall, LCS : http://www.lcsaudio.com -}

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From: Dave Baukus <[email-masked]>
Date: Fri, 12 Mar 1999 07:22:49 -0600

> new part numbers are 21281-xB.

The errata reads:
	"There is an anomaly in the SA-110 device that may occur during DATA_ABORT
	in environments that use demand-paging management schemes. This problem
	has been seen only in demand-page memory-management operating systems when
	a memory access crosses a page boundary from a mapped page to an  unmapped
	page during the sequence of data fetches."

It goes on to list some RTOSs that, since they do not use demand paging,
are not susceptible to the problem.

I heard that via a 3id party that and Intel rep. said Linux was not susceptible
to this problem. If true I'd like to know why. 

Any know the real answer ?

thanks.

--
Dave Baukus
	Inet Technologies Inc.
	[email-masked]

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From: Russell King - ARM Linux Admin <[email-masked]>
Date: Fri, 12 Mar 1999 16:50:26 +0000 (GMT)

> Any know the real answer ?

Any program in a demand paged OS would be susceptible to this problem.  However,
The Linux kernel itself is not.  The routines which use the ldm instruction are
carefully coded to handle the user space permissions anyway, so a ldm instruction
is never used to cross a page boundary.

It is, however, an issue for user programs.  The user stack is a conventional
full decending stack, which means that the affected instruction (ldmib) will not
be used.

Hence, I think the answer to this is that the ARM Linux OS is not susceptible
to this problem, but user programs could be.  My current experiance suggests that
no user programs currently exist which hit this problem.
   _____
  |_____| ------------------------------------------------- ---+---+-
  |   |        Russell King       [email-masked]      --- ---
  | | | |  http://www.arm.linux.org.uk/~rmk/armlinux.html    /  /  |
  | +-+-+                                                     --- -+-
  /   |               THE developer of ARM Linux              |+| /|\
 /  | | |                                                     ---  |
    +-+-+ -------------------------------------------------  /\\\  |
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From: Pat Beirne <[email-masked]>
Date: Fri, 12 Mar 1999 21:19:28 -0500

> no user programs currently exist which hit this problem.

I concur with Russell's statements.

We received Intel's errata in July. At that time, I investigated both the
code build environment, and the existing binary code. I, too, concentrated on
the kernel itself. In both cases, Russell is correct. [Of course he is; he wrote the
relevent code!]

I am not at all concerned with the existence of this errata, in terms of existing
code, and code which is being written. [ArmLinux only]

However, if people want to persue an experimental attack on SA-110 systems
to see where they break, I think that is a good idea.

BTW, someone asked about how do you tell chip rev numbers? The chip ID register
will return a 3 for S steppings (the ones that exhibit the errata). I have never seen

a T stepping (the new ones), but I assume the chip ID register will be incremented.

Pat
CorelComputer/HCC