Subject: Re: egcs 1.1.1 assembler output for 2.2. kernel compilation.

From: Russell King - ARM Linux Admin <[email-masked]>
Date: Sun, 7 Mar 1999 14:23:19 +0000 (GMT)

Richard Atterer writes:
> IMHO egcs really ought to produce 'ldrbt r6,[r6,#0]' instead of
> 'ldrbt r6,[r6],#0'.

However, ldrbt r6,[r6,#0] is not an encodable ARM instruction.
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From: Nicholas Clark <[email-masked]>
Date: Sun, 7 Mar 1999 15:07:21 +0000 (GMT)

In the last mail Richard Atterer said:

> In article <[email-masked]>
>     Russell King - ARM Linux Admin <[email-masked]> wrote:
> 
> > The ARM2 data book says:
> > 
> > 'In the case of post-indexed addressing, the write back bit is
> > redundant, since the old base value can be retained by setting the
> > offset to zero.'
> > 
> > Hence, when specifing an offset of zero, since no writeback is
> > performed, the result is predictable.  However, the question now is,
> > does this apply to the later processors?  Have ARM updated their ARM
> > to include this? Did they purposely remove this?  Or what?
> 
> I don't read the above quote as
> 
>   "if the offset is 0, no writeback is performed",
>   
> rather as
> 
>   "since 0 is added, it's as if no writeback had taken place".

Hmm. True.
The bit in '' is ambiguous. I'm inclined to agree with Russell, but I'd like to
see the text before it.
 
> Of course, interpretation may vary between processors. ;-) BTW, the RISC
> OS Appendix on ARM assembler also says:
> 
> "A post-indexed LDR|STR where Rm=Rn must not be used (this instruction
> is very difficult for the abort handler to unwind when late aborts are
> configured - which do not prevent base writeback)."
> 

Aah, you missed the point of my very brain-dead previous message (which 
enumerated the 4 possible states with 2 bits) - you can only do T with
post-indexed addressing.

Nick