Subject: Archimedes memory mapping question

From: Philip Blundell <[email-masked]>
Date: Sat, 17 Oct 1998 23:15:15 +0100

Does anybody know what the magic incantation is that causes the ROM shadow at 
address 0 to be turned off?  I'm assuming this is done by logic inside MEMC 
since IOEB is the only other likely-looking suspect and not all machines have 
that.

p.

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From: Russell King - ARM Linux Admin <[email-masked]>
Date: Sun, 18 Oct 1998 09:46:27 +0100 (BST)

Philip Blundell writes:
> address 0 to be turned off?

Yes.

> I'm assuming this is done by logic inside MEMC since IOEB is the only other
> likely-looking suspect and not all machines have that.

You're right that it isn't that.

Oh, I suppose you want to know ;)  You have to access a location below
0x01000000, and then a location above 0x02000000.  This will occur if
the first instruction in the reset vector jumps to the ROM.
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From: Ian Jeffray <[email-masked]>
Date: Sun, 18 Oct 1998 11:51:58 +0100 (BST)

> since IOEB is the only other likely-looking suspect and not all machines have 

ROM is only "mapped to address 0" when MEMC's RES (Reset) line is
asserted - this is because on a reset, vl86c0x0 starts executing from 0
and so this ensures ROM is accessed.   To restore the normal memory map,
the processor must perform a memory access with the address lines A25 and
A24 both low, then perform a memory access with the address line A25 high.
These conditions are satisfied when the processor starts executing
instructions from address 0, and later jumps to the normal ROM space.

Taken mostly from p4-9 of the Acorn Risc Machine Family Data Manual.

Hope that helps.

Ian
-- 
Ian Jeffray // Tel: 0131 337 9923 // Mobile: 0378 392 963 // [email-masked]

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From: Dave Gilbert <[email-masked]>
Date: Sun, 18 Oct 1998 12:21:07 +0100 (BST)

> since IOEB is the only other likely-looking suspect and not all machines have 

Yep - its the MEMC - thus speaketh the book of words (VL86C010 RISC Family
data manual'):

  'To restore the normal memory map, the processor must first perform a
memory access with the address lines A25 and A24 both low and then perform
a memory access with address line A25 high.  These conditions are
satisfied when the processor starts executing instructions from location
00000000H, and later jumps to the normal ROM space./'

Dave
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/ Dr. David Alan Gilbert      | Running Linux on Alpha(LX) |  Happy  \ 
\   gro.gilbert @ treblig.org |   & ARM(EBSA285,old Arc)   |  In Hex /
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From: Philip Blundell <[email-masked]>
Date: Thu, 22 Oct 1998 18:45:01 +0100

>Taken mostly from p4-9 of the Acorn Risc Machine Family Data Manual.

Yup.  Thanks to everybody who responded. :-)

p.