Subject: Re: cache flush on the sa110

From: Mark van Doesburg <[email-masked]>
Date: Mon, 7 Sep 1998 16:35:15 +0200

No it's not.  What's mapped at 0xfd000000 is the PCI outbound
	write flush area at 0x78000000.  The cache-flush area is set up
	by code in proc-armv/mm-init.h and is always at 0xdf000000 on
	all 32-bit architectures.

	p.

Oops, my mistake. Can we make this architecture dependent ?

Thanks,

Mark.
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From: Philip Blundell <[email-masked]>
Date: Mon, 07 Sep 1998 17:28:22 +0100

>Oops, my mistake. Can we make this architecture dependent ?

I don't see why not.  I think the code in mm/proc-*.S is pretty much all that 
cares.  You could move it to an arch/ include and mm-ebsa285 et al. if you 
wanted.

p.