Subject: cache flush on the sa110

From: Mark van Doesburg <[email-masked]>
Date: Mon, 7 Sep 1998 14:16:37 +0200

I've started implementing the architecture which can access all 4GB PCI
memory using the 21285. Among other things i had to relocate the SA-110
cache flush area (phys adr 0x50000000) this was mapped to 0xfd000000 on
the ebsa-285 architecture. When i look at linux/arch/arm/mm/proc-sa110.S
however i see the _sa110_flush_cache_all and the _sa110_switch_to
functions use;

	ldr rx,=0xdf000000

To load the address for the cache flush. I was expecting to see;

	ldr rx,=0xfd000000

Can anyone explain why it uses 0xdf000000 ? (or is it just a typing error ?)

Mark.
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From: Philip Blundell <[email-masked]>
Date: Mon, 07 Sep 1998 15:10:09 +0100

>the ebsa-285 architecture.

No it's not.  What's mapped at 0xfd000000 is the PCI outbound write flush area 
at 0x78000000.  The cache-flush area is set up by code in proc-armv/mm-init.h 
and is always at 0xdf000000 on all 32-bit architectures.

p.