Subject: Three questions...

From: Chris Sawer <[email-masked]>
Date: Thu, 24 Sep 1998 20:10:04 +0100

Hello again,

Three brief questions for those who know more about ArmLinux than I:

1. Is there going to be a complete elf release of ArmLinux for Acorn machines
at some point in the future? It would be really useful to have proper linked
executables, especially as some simple X applications (using the GTK) have
binaries several megabytes in size. Does more work need to be done on elf, or
is it just a case of someone spending a lot of time putting together the
distribution.

2. Does anyone else have problems with this mailing list - I keep being
thrown off it! The messages just stop coming, and I have to resubscribe every
week or so. This didn't used to be much of a problem as I could read the
archives on http://www.findmail.com/listsaver/linux-arm/ but this doesn't
seem to be kept up-to-date any more - has it been "unsubscribed"?

3. I'm /still/ trying to compile The Gimp, but my recompiled (statically
linked) ld from Binutils 2.8 gives this error:

ld: memory violation at pc=0x00031700, lr=0x6001ba80
(bad address=0x00000004, code 3)
gcc: Internal compiler error: program ld got fatal signal 11

Does anyone understand this at all?

Thanks in advance for any help,

Chris

-- 
  Chris Sawer - Worthing, Sussex, England
    http://members.xoom.com/chrissawer/
E-Mail: [email-masked],  ICQ: 15010147
    PGP public key available on request
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---

From: Philip Blundell <[email-masked]>
Date: Fri, 25 Sep 1998 11:06:00 +0100

>is it just a case of someone spending a lot of time putting together the

The Debian people are working on an ELF-based distribution.  It should work on 
Acorn machines without too much trouble.  I don't know what the current status 
is though.

We're almost at the stage where it's just a case of someone putting in the 
time and cycles to build all the packages.  But there are a couple of things 
that need sorting out in the ELF tools first.  Jim Pick is working on this.

>thrown off it! The messages just stop coming, and I have to resubscribe every

Your mail is probably bouncing.

>Does anyone understand this at all?

The linker tried to dereference NULL.

p.

---

From: Russell King - ARM Linux Admin <[email-masked]>
Date: Fri, 25 Sep 1998 19:46:58 +0100 (BST)

> seem to be kept up-to-date any more - has it been "unsubscribed"?

I don't see why this is happening - I haven't received any bounces from the
list for usa.net since 24 June, when there was a major DNS failure on the
Internet (and that produced a 55k non-delivery report for almost everyone
on the list).

As far as the subscription/unsubscription records go, you've subscribed on:

Jul 10, Aug 30, Sep 17, Sep 22

and unsubscribed on:

Jul 23

Maybe vger's having an argument with you?  I'll mail the majordomo owner
and find out what's going on...

Does anyone else have this problem?
   _____
  |_____| ------------------------------------------------- ---+---+-
  |   |        Russell King       [email-masked]      --- ---
  | | | |  http://www.arm.uk.linux.org/~rmk/armlinux.html    /  /  |
  | +-+-+                                                     --- -+-
  /   |               THE developer of ARM Linux              |+| /|\
 /  | | |                                                     ---  |
    +-+-+ -------------------------------------------------  /\\\  |
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---

From: Jim Pick <[email-masked]>
Date: 25 Sep 1998 15:00:53 -0700

Philip Blundell <[email-masked]> writes:

> The Debian people are working on an ELF-based distribution.  It
> should work on Acorn machines without too much trouble.  I don't
> know what the current status is though.

I don't see why it wouldn't work.  I don't know of anybody that has
tried in on a non-NetWinder machine (if you supply your own kernel -
we don't have one yet).  I'd like to see it running on an Acorn box.

(any volunteers?)

  http://www.debian.org/ports/arm/

We have a chroot image - it should be possible to pop it into a
directory on a Linux/ARM machine (with ELF executable support) to see
if it will run.

The project has stalled a bit in the last few weeks as everybody waits
for me to put out a new glibc.  Hopefully things will start moving
again soon.

Cheers,

 - Jim

---

From: Stefan Hanske <[email-masked]>
Date: Mon, 28 Sep 1998 16:30:41 +0200 (METDST)

> for me to put out a new glibc.  Hopefully things will start moving

Most of the things should work - but on a StrongARM RiscPC only. Since 
I've got an ARM710 there'll be no chance using the binary packages on my 
system.

----------------------------------------------------------
|mailto: Stefan Hanske ([email-masked] |
|WWW : http://www.rzuser.uni-heidelberg.de/~shanske      |
|phone: I'm not silly                                    |
|--------------------------------------------------------|
| And don't forget to remember what you remembered not   |
| to forget to remember...				 |
----------------------------------------------------------

---

From: Philip Blundell <[email-masked]>
Date: Mon, 28 Sep 1998 16:24:27 +0100

>I've got an ARM710 there'll be no chance using the binary packages on my 

Once everything is working on StrongARM it will be a no-brainer operation to 
recompile everything with the right CFLAGS for ARM710.  In fact the NetWinder 
packages won't even work on a StrongARM RiscPC because of the halfword 
problem.  They should be OK out of the box on an EBSA or similar.

p.

---

From: Richard Bradbury <[email-masked]>
Date: Mon, 28 Sep 1998 17:08:24 +0100

On Mon, 28 Sep 1998 16:30:41, Stefan Hanske wrote:
> I've got an ARM710 there'll be no chance using the binary packages on
> my system.

This seems an important point.  Can't the Red Hat and Debian people be
persuaded to precompile generic binaries suitable for ARM6/7 processors
as well as version 4 architecture CPUs like the StrongARM?

What is so wonderful about the halfword instructions that makes them so
desirable?  Would there really be much of a performance hit in
refraining from using them for the sake of wider compatability?

-- 
Richard.

---

From: Vincent Renardias <[email-masked]>
Date: Mon, 28 Sep 1998 18:45:31 +0200 (CEST)

> as well as version 4 architecture CPUs like the StrongARM?

Speaking as a Debian developer and Acorn RPC600 owner:
I can't talk for RedHat, but the Debian x86 distribution is compiled
for i386, and I certainly hope the ARM version will run on ARM6/7
processors too.

	Cordialement,

-- 
- Vincent RENARDIAS    vincent@{{waw,pipo}.com,{debian,openhardware}.org} -
- Debian/GNU Linux:        Open Hardware:              WAW:               -
- http://www.fr.debian.org http://www.openhardware.org http://www.waw.com -
---------------------------------------------------------------------------
-"Depuis que ma voiture et mon ordinateur tournent au GPL, les 2 marchent -
- beaucoup mieux et pour moins cher... (Linux: Le seul OS non-polluant!)" -

---

From: Eduard Pfarr <[email-masked]>
Date: Mon, 28 Sep 1998 18:55:01 +0200

»Philip Blundell« schrieb in Artikel
<[email-masked]> folgendes:

> Once everything is working on StrongARM it will be a no-brainer operation
> to recompile everything with the right CFLAGS for ARM710.

Hopefully.

I wouldn't say »no-brainer operation« though. It really has to be simple
and easy to get Linux and programs to work. Because for many people (the
number increases rapidly) there's no reason to dive into Linux' internas
when they really just want to work on it in order to do their every-day-
tasks.

 Cheers,
 Eduard.

-- 
Wunschliste Linux-Software: http://linuxresources.com/wish/
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---

From: Jim Pick <[email-masked]>
Date: 28 Sep 1998 10:37:58 -0700

> problem.  They should be OK out of the box on an EBSA or similar.

I'm wondering what we should do for the Debian port to support more
machines than just the NetWinder.

Right now, we've built gcc with the --with-cpu=strongarm option, and
we are compiling all the packages with the normal CFLAGS options.
We're using the Corel patched gcc right now, but plan on moving to
Philip's egcs.

So I suppose we are building binaries that use the halfword
instructions.  Is that correct?

In the interests of portability, what would be the performance cost if
we somehow compiled things without the halfword instructions?  Do all
apps benefit, or just some specific ones?  Corel is using them for
their RPM-based distribution, so I have assumed that there is a
significant performance difference.

As Philip says, it would be a no-brainer to create additional
debian-arm distributions which have been compiled to use different
instruction sets, since they can share the same source (actually, all
Debian architectures use the same source).  ie. We could have an
"arm-riscpc" distribution, and maybe even an "arm-710" (??)
distribution for older machines.  Of course, this is only going to
happen if there is enough interest.

This isn't without precedence - there is a sparc and a sparc64
distribution, and there has been much talk about how to build a
Pentium-optimized distribution, where just some packages are
optimized, and the rest would be symlinked to the i386 distribution.

If anybody wants me to, I could build a chroot image and a set of
packages that have been compiled to use a different instruction set
and put them on my FTP site.

Is anybody interested in such a thing?  There isn't much point in me
doing it if nobody is going to try it, since I don't have the hardware
to test it on.

I suppose I can lookup what flags to use from the source for the
Linux/ARM distribution.  Or maybe somebody could tell me?

Cheers,

 - Jim

---

From: Philip Blundell <[email-masked]>
Date: Mon, 28 Sep 1998 19:05:33 +0100

>instructions.  Is that correct?

Yes.  If you use -march=armv4 (or -mcpu=strongarm110 which implies it) then 
you will be using the halfword instructions.

>significant performance difference.

The halfword instructions probably do make a measurable difference.  More to 
the point the v4 architecture introduces instructions like UMULL which can 
make even more of a difference and you can't (currently at least) selectively 
enable these.

I don't think there's much to be gained from compiling the standard Debian 
packages with backwards-compatibility options.  The number of ARM machines 
that can't run v4 binaries is fairly small and likely to stay that way.  If 
someone wanted to produce a CD with appropriate binaries for older machines 
there would be nothing to stop them.

>Linux/ARM distribution.  Or maybe somebody could tell me?

-mcpu=arm6 will work on all v3 and later machines.

p.

---

From: Matthew Wilcox <[email-masked]>
Date: Mon, 28 Sep 1998 20:28:14 +0200

> instructions.  Is that correct?

Yes.  You can always objdump --disassemble |grep LDRH to check ;-)

> significant performance difference.

I don't think there's too much of a performance issue.  One or two
additional instructions per short loaded, two extra ones per short
stored.

> happen if there is enough interest.

you'd almost certainly want to use arm6 as the baseline - arm710 doesn't
have anything that needs changing in userland.

> doing it if nobody is going to try it, since I don't have the hardware

Yes, I'm willing to test..

> Linux/ARM distribution.  Or maybe somebody could tell me?

It was -m6 for gcc 2.7, but egcs & gcc 2.8 moved to -march=3.
Or something similar, my GCC docs are out of date right now and I can't
test easily.

-- 
Matthew Wilcox <[email-masked]>
"I decry the current tendency to seek patents on algorithms.  There are
better ways to earn a living than to prevent other people from making use of
one's contributions to computer science."  -- Donald E. Knuth, TAoCP vol 3
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---

From: Philip Blundell <[email-masked]>
Date: Mon, 28 Sep 1998 19:44:53 +0100

>Hopefully.
>
>I wouldn't say =BBno-brainer operation=AB though. It really has to be
>simple

I wasn't suggesting that *users* should do this.  (If they need to recompile, 
they can't even boot enough of a system to run the compiler!)  But since 
ARM7 needs no source-level changes compared to StrongARM it's just a question 
of someone with access to all the package sources going through and recompiling 
the .deb files for the right CPU.  I imagine it would be an entirely 
automatic process and someone with only a modest amount of knowledge could do 
it.

p.

---

From: Philip Blundell <[email-masked]>
Date: Mon, 28 Sep 1998 19:47:30 +0100

>That makes it sound like it would be best to have two distributions.
>One optimized for the new StrongARM-based machines that can handle the
>halfword instructions (ie. NetWinder, EBSA).  And a
>"lowest-common-denominator" distribution that uses the ARMv3
>instruction set (for the ARM710, and RiscPC).

I agree.  And if somebody was sufficiently sick they could even have a go at 
building a 26-bit version for the ARM3. :-)

>make a chroot image so people can play with it.  How does "armv3"
>sound for a distribution name (vs. "arm", which we are using for the
>NetWinder stuff)?

Sounds fine.

p.

---

From: Jim Pick <[email-masked]>
Date: 28 Sep 1998 11:48:31 -0700

> The halfword instructions probably do make a measurable difference.
> More to the point the v4 architecture introduces instructions like
> UMULL which can make even more of a difference and you can't
> (currently at least) selectively enable these.
> 

> -mcpu=arm6 will work on all v3 and later machines.

Thanks.  That sounds simple enough to do.  When I get some time over
the next few days, I'll try recompiling the base system for ARMv3, and
make a chroot image so people can play with it.  How does "armv3"
sound for a distribution name (vs. "arm", which we are using for the
NetWinder stuff)?

Cheers,

 - Jim

---

From: Jim Pick <[email-masked]>
Date: 28 Sep 1998 12:02:13 -0700

> Yes.  You can always objdump --disassemble |grep LDRH to check ;-)

Confirmed.
 
> additional instructions per short loaded, two extra ones per short

Hmm.  Philip thought there was a significant difference.  Maybe the
best thing for me to do is to try compiling each, and do some
benchmarking.

Right now, I'm inclined to believe that the performance differential
between the new ARM stuff and the old (obsolete?) ARM stuff is large
enough to merit two binary distributions.
 
> have anything that needs changing in userland.

Ok.

> Yes, I'm willing to test..

Great!

I'll try to have something ready by the end of the week.  I want to
get glibc 2.0.96 working first (I'm having some problems with that).

Cheers,

 - Jim

---

From: Eduard Pfarr <[email-masked]>
Date: Mon, 28 Sep 1998 22:20:26 +0200

»Philip Blundell« schrieb in Artikel
<[email-masked]> folgendes:

> I agree.

I can't agree. Since StrongARMed RiscPC's are the only Acorn boxes where
Linux runs attractively on, I think a StrongARM optimized version without
halfword instructions (because of the RiscPC's bus) is quite neccessary

---

From: Eduard Pfarr <[email-masked]>
Date: Mon, 28 Sep 1998 23:02:34 +0200

»Philip Blundell« schrieb in Artikel
<[email-masked]> folgendes:

[..]
> I don't think there's much to be gained from compiling the standard
> Debian packages with backwards-compatibility options.  The number of
> ARM machines that can't run v4 binaries is fairly small and likely to
> stay that way.

Some ten thousands from Acorn. Because Acorn dropped its own OS I bet that
loads of people move to (Acorn-) ARM-Linux in the very near future.

I'd be very interested in exact numbers: How many of these Acorns have got
a StrongARM? Personally speaking I hardly know any Acorn RiscPC user who
hasn't upgraded to StrongARM, so I guess: Quite many StrongARMed Acorns

---

From: Jim Pick <[email-masked]>
Date: 28 Sep 1998 14:57:47 -0700

Scott Bambrough <[email-masked]> writes:

> Yes.  They are automatically enabled with -mcpu=strongarm.  The NetWinder
> requires -march=armv4 to ensure some cpu cache issues are handled correctly,
> however, the cpu could be left as default.
> 
> Not in my experience.  The halfword and signed byte instructions are only 
> emitted with -O2.  The basic code generator does not emit them, only the 
> optimizing pass.They are used to speed up access to shorts, and signed
> characters if I remember correctly.  They do speed things up, it takes 
> one two cpu cycles to access shorts without them and three to access 
> signed bytes if I recall correctly.    
> 
> I chose to configure gcc with -with-cpu=strongarm to generate code that
> would be most efficient on the NetWinder.

I think I may be confused about what constitutes a "RiscPC".

I thought they all had StrongARM CPUs, but I think I was wrong.
Acorn's web site isn't much help.

I see there is the Acorn RiscPC 600 series, Acorn RiscPC 700 series,
and then the Acorn StrongARM RiscPC.  I am guessing that the 600 and
700 series are using chips that only support the armv3 instruction
set?  If that's the case, then those are RiscPCs, but they can't
handle halfword instructions.  But the StrongARM RiscPC can handle the
halfword instructions, right?

I was getting confused when people said that RiscPCs couldn't handle
the halfword instructions, because I initially thought that all RiscPC
models were using the StrongARM.

If that's the case, then we have a pretty clean split between armv3
machines, and StrongARM machines (NetWinder, EBSA, and StrongARM
RiscPC).  Then the current Debian "arm" distribution should be work on
any StrongARM based machine, including the StrongARM RiscPC.  The
RiscPC 600, 700 and some older models will need to use the "armv3"
distribution.

Or do I still have it wrong?

Cheers,

 - Jim

---

From: Richard Bradbury <[email-masked]>
Date: Mon, 28 Sep 1998 23:06:43 +0100

> sound for a distribution name (vs. "arm", which we are using for the

That sounds great.  Can't wait to try it out on my "obsolete" ARM610
and ARM710 RiscPCs :-)

Does the above indicate the prospect of an offical ARM v3 distribution
of Debian at some point in the future?  From recent postings to this
list, there seems to be pent up demand for a full ELF Linux
distribution suitable for installing on the RiscPC with 610/710/SA110.

As a separate issue, what is going to happen when ARM Linux starts to
make a mark on the radar screens of big boys like Oracle, Corel,
Netscape or even Microsoft?  My guess is that it's going to be a
"sorry, ARM v4 only, folks" story here.  Even those lucky enough to
have a StrongARM RiscPC will be frozen out because of the halfword
instruction problem.

-- 
Richard.

---

From: Philip Blundell <[email-masked]>
Date: Mon, 28 Sep 1998 23:29:17 +0100

>and then the Acorn StrongARM RiscPC.  I am guessing that the 600 and

They are all the same basic machine.  You can plug in a CPU card with either a 
610, a 710 or an SA110 on.

>halfword instructions, right?

No.  The RiscPC glue logic can't handle 16-bit transfers at all.  It was 
originally designed with the ARM6 in mind.

p.

---

From: Philip Blundell <[email-masked]>
Date: Mon, 28 Sep 1998 23:44:52 +0100

>Hmm.  Philip thought there was a significant difference.  Maybe the

I must admit that when I originally wrote that I was still in kernel mode and 
thinking of code that has -mshort-load-bytes enabled.  When the load-rotate 
trick can be used the cost is somewhat lower -- though, I suspect, still 
not negligible.  This doesn't apply to stores, obviously.

p.

---

From: Philip Blundell <[email-masked]>
Date: Tue, 29 Sep 1998 00:01:37 +0100

>As a result, half-word (and possibly load signed byte?) instructions
>do not work.

I imagine signed byte is OK; it probably consists of just a ldrb followed by a 
sign-extend and the latter is internal to the processor.

p.

---

From: Melanie Rhianna Lewis <[email-masked]>
Date: Tue, 29 Sep 1998 00:07:42 +0100 (BST)

On Mon, 28 Sep 1998, Eduard Pfarr wrote:

> hasn't upgraded to StrongARM, so I guess: Quite many StrongARMed Acorns.

Well mine hasn't been upgraded and is unlikely too as I have other
priorities (motor bikes!).  Its still a basic RPC600 except with a SCSI
card, 32Mb ram and 2Mb VRAM.  Its perfectly usable and runs about the same
speed as my girlfriend's 486DX66 running Linux.  Its also a perfect
compliment to my P166 Linux box.

I would quite like a Debian/ELF release thanks.  If I want strong arm I'll
get a netwinder.

Melanie

-- 
=====================================================================
Melanie Rhianna Lewis                      [email-masked]
"An it hurt none, do what thou will"    http://www.defaid.demon.co.uk
         TLBB#2 TGMCC#1 - MZ125, X7 (Under re-construction) 
=====================================================================

---

From: Jim Pick <[email-masked]>
Date: 28 Sep 1998 16:12:27 -0700

> They are all the same basic machine.  You can plug in a CPU card
> with either a 610, a 710 or an SA110 on.

Ok.  I didn't know that.

Please excuse my ignorance - I couldn't find much good info on the
web.  Maybe I should have read more of the mailing list archives.
 
> originally designed with the ARM6 in mind.

Hmm.  Since it doesn't sound like there is going to be a big penalty
for not using the halfword instructions, I'd like to not use them so
that the StrongARM RiscPC users could use the Debian "arm"
distribution.  People with armv3 processors (ie. RiscPC 600, 700) could
use the "armv3" distribution.

How do I do that?  If I configure gcc using --with-cpu=strongarm, I'm
going to get the halfword instructions.  Is there another option I can
use?  ie. --with-cpu=armv4?  Or is this going to require patching gcc?

Or perhaps the StrongARM RiscPC is so rare, it's not worth decreasing
performance for the other StrongARM machines (like the NetWinder)?
The StrongARM RiscPC people would still be able to use the "armv3"
distribution.  What proportion of Linux/ARM users have the Acorn
StrongARM RiscPC?

Cheers,

 - Jim

---

From: Philip Blundell <[email-masked]>
Date: Tue, 29 Sep 1998 00:13:46 +0100

>use?  ie. --with-cpu=armv4?  Or is this going to require patching gcc?

Basically you can't at the moment.  It wouldn't be any big deal to add an 
option to gcc to inhibit halfword instructions but allow all other ARMv4 
enhancements, but so far I haven't done it because there's been no pressing 
need and it seemed like a needless complication.  Feel free to make a patch to 
egcs to implement this; it might make life slightly easier for the Acorn 
people.

>performance for the other StrongARM machines (like the NetWinder)?

To be honest I think this is the case.  The number of Acorn machines running 
Linux is really pretty small.  Since most future ARM machines are likely to 
support halfwords and the like it seems sensible to go with that as the 
default.

p.

---

From: Jim Pick <[email-masked]>
Date: 28 Sep 1998 16:22:24 -0700

Matthew Wilcox <[email-masked]> writes:

> Sorry, it's not nearly that simple.  Can we have a debian-arm and a
> debian-acorn distribution, otherwise people will be confused.  People
> would have been more confused had Phoebe ever made it into production.
> (This would be an Acorn machine which supported the StrongARM properly)

We could call the "armv3" distribution an "arm-acorn" distribution.
That might make sense, especially if we decide to use halfword
instructions for the "arm" version, so it wouldn't run on any of the
Acorn machines.

Of course, that might not be a good name, because Acorn could release
something in the future based on the StrongARM.  Also, there might be
non-Acorn machines that need the armv3 stuff.

Cheers,

 - Jim

---

From: Matthew Wilcox <[email-masked]>
Date: Tue, 29 Sep 1998 01:34:45 +0200

> instructions for the "arm" version, so it wouldn't run on any of the

That's what I was thinking.  Is there more confusion saying `The armv3
distribution is for all ARM6 & ARM7 machines, plus the Acorn RiscPC
with StrongARM', or saying `The acorn distribution is for all Acorn
machines, plus anything less than a StrongARM'?  Thinking about it,
I guess I'm wrong.  The easiest thing to do is to cope with people
complaining that the `arm' distribution doesn't work on their RiscPC,
rather than cope with people saying `but my machine isn't an acorn'
Damn, I hate hardware ;-)

> non-Acorn machines that need the armv3 stuff.

Hadn't you heard?  Acorn have dumped their Workstation division and
laid off 75 employees :-(  They announced their future lies in Set Top
Boxes and Digital TV, and I don't see much scope for running a Debian
distribution on those.  You may be right about other companies producing
ARMv3 designs - the Psion 5 _may_ be, but on the other hand it might
be based on an ARM7TDMI which is an ARMv4 architecture.  I honestly
can't remember.

---

From: Matthew Wilcox <[email-masked]>
Date: Tue, 29 Sep 1998 01:34:45 +0200

---

From: Jim Pick <[email-masked]>
Date: 28 Sep 1998 16:45:56 -0700

> distribution suitable for installing on the RiscPC with 610/710/SA110.

Well, I'll prepare an initial "unofficial" set of packages for
"armv3", so people will be able to give it a try.  People can try them
out by setting up a chroot environment.

Myself, I own a NetWinder, so that's what I am going to concentrate
on.  So I won't do much beyond compiling the base system for armv3
(minus the kernel).  If there is any interest, it wouldn't be too much
work for people with RiscPCs to compile binaries for an official
"armv3" distribution.  I'm sure Vincent Renardias (one of the key
Debian maintainers, who also has a RiscPC 600) would be interested in
this - so we have at least one user.  :-)

> have a StrongARM RiscPC will be frozen out because of the halfword

That's primarily an issue for binary-only packages (ie. Corel
WordPerfect).  I suspect that might be true.  The StrongARM RiscPC
folks might want to petition Corel to compile WordPerfect without
halfword instructions.

Cheers,

 - Jim

---

From: Jim Pick <[email-masked]>
Date: 28 Sep 1998 16:55:53 -0700

> support halfwords and the like it seems sensible to go with that as the 

And the StrongARM RiscPC users would still be able to use the "armv3"
distribution.

I think what I will do is go ahead and build the "armv3" stuff --
which will work on an ARM6 CPU or better.  The StrongARM RiscPC users
can use that distribution as well for now.  If there is truly enough
demand, somebody could do an "arm-riscpc-sa" distribution, or modify
the gcc in the "arm" distribution so that it doesn't use the halfword
instructions.

I'll try to get the "armv3" stuff ready by the end of this week
(unless I have too much trouble with glibc 2.0.96).

Cheers,

 - Jim

---

From: Scott Bambrough <[email-masked]>
Date: Tue, 29 Sep 1998 01:18:11 -0400

> refraining from using them for the sake of wider compatability?

I wouldn't blame the Debian people for the choice of compiling their binaries
with halfword instructions.  For the most part, they started out with a
NetWinder
and development tools provided by me and I was the guy who made that choice.  I
wasn't concerned about wider compatibility, just making the NetWinder do its 
very best.  Too my knowledge, RedHat provides no ARM binaries of any kind.  The
only
sources of RPM's are Russell King's site and netwinder.org.
unsubscribe: body of `unsubscribe linux-arm' to [email-masked]

---

From: Scott Bambrough <[email-masked]>
Date: Tue, 29 Sep 1998 04:06:03 -0400

Scott

---

From: James Craig <[email-masked]>
Date: Tue, 29 Sep 1998 09:37:38 +0100 (BST)

> be based on an ARM7TDMI which is an ARMv4 architecture.  I honestly
<fishes out his Psion 5>
<goes to machine hardware page>
Processor: ARM7100
Speed: 18.432MHz.
ROM: 6M
RAM: 8M
So there you go. I think it's pretty similar to the ARM7500 but designed
for a palmtop instead of a normal PC.

--
James Craig <[email-masked]>
            <[email-masked]>

---

From: Eduard Pfarr <[email-masked]>
Date: Tue, 29 Sep 1998 10:51:14 +0200

»Philip Blundell« schrieb in Artikel
<[email-masked]> folgendes:

Hallo,

> enhancements, but so far I haven't done it because there's been no
> pressing need and it seemed like a needless complication.  Feel free to
> make a patch to egcs to implement this; it might make life slightly
> easier for the Acorn people.

Naturally it will make life easier for us Acorn StrongARM users. Please do
that patch <g>.

The StrongARM has many pros compared to older ARMs (you know I know <g>) so
disabling the StrongARM features on Acorn StrongARM machines »just« because
they can't handle the halfword operations makes the computers much slower
than they should.

> To be honest I think this is the case.  The number of Acorn machines
> running Linux is really pretty small.

Since Acorn's native OS (RISC OS) isn't supported any longer the number of
Acorn users running Linux will increase. I don't know numbers right now but
I know there are many Acorn StrongARM users out there. Because they won't
throw away their machines they'll have to use ARM Linux.

> Since most future ARM machines are likely to support halfwords and the
> like it seems sensible to go with that as the default.

Since Linux supports all kind of different architectures it looks to be
a bit unfair to ignore the Acorn StrongARM RiscPC machines which have got a
CPU clocked six times higher than any older Acorn ARM6xx/7xx RiscPC together
with an improved instruction set (MULs etc)... :-|

 Cheers,
 Eduard.

---

From: Phil Norman <[email-masked]>
Date: Tue, 29 Sep 1998 09:58:46 +0100

In message <[email-masked]>
          Eduard Pfarr <[email-masked]> wrote:

> Philip Blundell schrieb in Artikel
> halfword instructions (because of the RiscPC's bus) is quite neccessary.

I'd like you to remember a few things.  Firstly, these guys gain nothing for
compiling up a RiscPC version at all, so it's rather nice of them to do that
much.  Secondly, Acorn machines are occupying a smaller and smaller position
in the linux-arm scene, and so support for RiscPCs is becoming less
important.  Thirdly, due to the ridiculously slow bus on a StrongARM RiscPC,
unix-clone OSs run incredibly slowly anyway (they tend to require fast busses
far more than RiscOS does).

So basically what I'm trying to say is, stop complaining and be content with
what Jim is already doing, at no gain to himself, for the benefit of those
with RiscPCs.

Phil

---

From: Eduard Pfarr <[email-masked]>
Date: Tue, 29 Sep 1998 11:01:10 +0200

»Jim Pick« schrieb in Artikel
<[email-masked]> folgendes:

Hallo,

[..]
> folks might want to petition Corel to compile WordPerfect without

Unfortunately we StrongARM RiscPC users don't have a real lobby/company
behind us so I'm pretty pessimistic about such a petition. The Europeans
look to be conservative when it comes to Internet petitions done by the
users... <g>

So in the end even with Linux OS I've to own either a Wintel box or a
Netwinder in order to run binary-only software. Sigh. Funny point: Most of
us StrongARM RiscPC users already had a StrongARM when the world hardly
knew what the ARM and StrongARM actually is... <g>

 Cheers,
 Eduard.

---

From: Eduard Pfarr <[email-masked]>
Date: Tue, 29 Sep 1998 11:40:40 +0200

»Phil Norman« schrieb in Artikel
<[email-masked]> folgendes:

Hallo,

> > Linux runs attractively on, I think a StrongARM optimized version
> > without halfword instructions (because of the RiscPC's bus) is quite
> > neccessary.
> 
> I'd like you to remember a few things.  Firstly, these guys gain nothing
> for compiling up a RiscPC version at all, so it's rather nice of them to
> do that much.

Yes, definitely!
Still there's no need to »remember« me because I didn't ignore it. I just
participate at a discussion here. <g>

> Secondly, Acorn machines are occupying a smaller and smaller position
> important.

Yes and no - RiscPC users could replace their dieing RISC OS with Linux
(like many Amiga users did with AmigaOS). If the RiscPC-II should ever
enter the market it would run Linux, too.

> Thirdly, due to the ridiculously slow bus on a StrongARM RiscPC,
> unix-clone OSs run incredibly slowly anyway

I've read Linux runs happily on 386 and 486 Wintel boxes which usually
don't have a faster bus so I'm not sure what you're trying to say... <g>

> So basically what I'm trying to say is, stop complaining and be content
> with what Jim is already doing, at no gain to himself, for the benefit of
> those with RiscPCs.

I'd like you to remember that Jim asked which ARM releases he should do

---

From: Mark Koek <[email-masked]>
Date: Tue, 29 Sep 1998 11:49:15 +0200

> I would quite like a Debian/ELF release thanks.  If I want strong arm I'll

Mine *is* upgraded (anyone need a spare ARM610? :-). However, having
read this thread I don't think it's worth the trouble to create a
strongarm-without-LDRH/STRH-distribution, because the only benefit of
that compared to an armv3 distribution would be the long multiply
instructions.

What code would be generated for ARM6/7 where a StrongARM would use a
64bit multiply? Is it very 'expensive'? Plus, how often are those
instructions actually used in practice?

Mark Koek

PS How about a distribution for my old ARM2-machine? ;-)
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---

From: David Alan Gilbert <[email-masked]>
Date: Tue, 29 Sep 1998 11:15:54 +0100

James Craig wrote:
> That someone else had written (Possibly Matthew)

<stuff removed>

>  You may be right about other companies producing

I >think< that any ARM7 design is V3; or V3T if it has a Thumb extension.
StrongARM, ARM8 etc are V4 with the snazzy load extension.

> for a palmtop instead of a normal PC.

I think there are some people who've looked at porting to Psion; but I haven't
heard anything from them lately.

Dave
-- 
----------------------------------------------------------------------
- Dr. David Alan Gilbert - WARNING! This is a beta release .signature-
- Work:    dg @ cogency.co.uk        - +44-(0)161-428-9444           -
- Home:    gro.gilbert @ treblig.org -                               -
----------------------------------------------------------------------
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---

From: Stefan Hanske <[email-masked]>
Date: Tue, 29 Sep 1998 12:44:20 +0200 (METDST)

> this - so we have at least one user.  :-)

I think there's two at least... and there'll be a lot more. Since Acorn's 
RiscPCs aren't like normal PCs (they do work fine for 5 years without the 
need to upgrade yearly), there is definitly a "market" for an armv3 
distribution of at least a basic system including basic tools / X11R6 / 
some libraries.

---

From: Russell King <[email-masked]>
Date: Tue, 29 Sep 1998 12:04:58 +0100 (BST)

Phil Norman said:
> much.

Another point to remember - I gain very little from Linux as well (in fact, I
end up with a lot of grief, but that's my choice when I created Linux on ARM).

> in the linux-arm scene, and so support for RiscPCs is becoming less

Especially now with Acorn Workstation gone.  However, IMHO they are still a
viable machine from my perspective at the moment.  Although I'm starting to
put more effort into the EBSA-285 port (giving it a HD for starters), my main
machine will still be the RiscPC for some time yet.

> Thirdly, due to the ridiculously slow bus on a StrongARM RiscPC, unix-clone
> OSs run incredibly slowly anyway (they tend to require fast busses

So far, since adding the hard drive to the EBSA-285 last night, I have not
achieved the performance from it that I was hoping for - the transfer rate
off of the HD is 1.2MB/s - slower than the RiscPC!  This is a Promise UltraDMA
card with the Conner 1GB drive from the RiscPC.  On the RiscPC, I managed to get
1.6MB/s out of it.

I am still hopeful to get the speed up on the EBSA, so don't take these figures
as fact yet.

> what Jim is already doing, at no gain to himself, for the benefit of those

Indeed, and report bugs with information on how they're caused ;)

--
Russell King ([email-masked])
Millbank Electronics Tel: 01825 764811 Fax: 01825 761620
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---

From: Hugo Fiennes <[email-masked]>
Date: Tue, 29 Sep 1998 12:28:19 +0100 (BST)

> for a palmtop instead of a normal PC.

It's an ARM7 core, yes, with 8k of cache (as opposed to 4k on the 7500?).
If you telnet to ham01.dcs.warwick.ac.uk, you'll see one running Linux :-)
(holdups on the Psion5 port: mainly, the chips they use are organised in
such a way that you only get 512k contiguous with MMU off. Kernel wasn't
happy running in that sort of space when last tried :-(

The board you can telnet to is my wirewrapped '7100 board, with a proper
symmetrical row/column SIMM.

Hugo

-- 
Disclaimer: "The contents of this albatross were measured by weight, not
volume. Contents may have settled during transit."

---

From: Philip Blundell <[email-masked]>
Date: Tue, 29 Sep 1998 14:27:37 +0100

>PS How about a distribution for my old ARM2-machine? ;-)

Nobody has done the work to make ELF run on 26-bit machines yet.  It's 
certainly not impossible and it's something I plan to look at eventually but 
as priorities go it's quite low down.

p.

---

From: Matthew Wilcox <[email-masked]>
Date: Tue, 29 Sep 1998 15:38:46 +0200

> they can't handle the halfword operations makes the computers much slower

Really?  You know this for a fact do you?

I don't think many programs use shorts.  To check my guess, I just
untarred the grep-2.2 package from Debian, and grepped all the files.
Not one single `short' in it.  It may be atypical, but on the other
hand I can't remember the last program I wrote that used a short.

I don't know under what circumstances GCC will produce the MULL opcode.
probably only when using `long long'.  A grep through the grep code
again produces _no_ `long long' usage either.

What other extensions does armv4 have over armv3?  I'd like to know
there's a real problem before actually worrying about it.  One question
I have is whether GCC will generate code which _won't_ run on a SA?
I'm referring to unusual things like relying on PC+8/PC+12 issues; I very
much doubt it generates this code, or that it generates self-modifying
code, but I'd like to be sure.

> with an improved instruction set (MULs etc)... :-|

I really don't think the extra instructions get you terribly much more
in the way of performance for real life applications.  They may well
suit embedded applications and produce significant enhancements there,
since that is ARM's target market.

---

From: Philip Blundell <[email-masked]>
Date: Tue, 29 Sep 1998 15:47:05 +0100

>off of the HD is 1.2MB/s - slower than the RiscPC!  This is a Promise UltraDMA

That certainly is a bit dismal.  I must admit I never did any testing to see 
how fast the CATS hard drive was.  I'll have to give it a go.

p.

---

From: Matthew Wilcox <[email-masked]>
Date: Tue, 29 Sep 1998 17:16:07 +0200

> instructions actually used in practice?

Good question.  A naive implementation gives me 12 instructions:

mov   r2, r0, lsr #16
bic   r0, r0, r2, lsl #16
mov   r3, r1, lsr #16
bic   r1, r1, r3, lsl #16
mul   r4, r0, r1
mul   r0, r3, r0
mul   r1, r2, r1
mul   r2, r3, r2
adds  r4, r4, r0, lsl #16
adc   r2, r2, r0, lsr #16
adds  r0, r4, r1, lsl #16
adc   r1, r2, r1, lsr #16

This uses 3 additional registers, and it probably has some nasty stalls
while waiting for mul to complete.  I suspect other people have done
better.  However, i don't believe these instructions are used terribly
often, as I said in my earlier post.

> PS How about a distribution for my old ARM2-machine? ;-)

Once I get my R140 out here, I'll look into it.  But I don't think we
should burden Debian with having to create a distribution.  Particularly
since there's no armv2-ELF solution yet.

---

From: Philip Blundell <[email-masked]>
Date: Tue, 29 Sep 1998 17:34:02 +0100

>hand I can't remember the last program I wrote that used a short.

FWIW, I've been working with Bison this afternoon and the parsers it generates 
use shorts all over the place.

>I have is whether GCC will generate code which _won't_ run on a SA?

I don't think so.

p.

---

From: Russell King - ARM Linux Admin <[email-masked]>
Date: Tue, 29 Sep 1998 22:37:29 +0100 (BST)

> instructions for the "arm" version, so it wouldn't run on any of the

I would strongly suggest calling the ARM for acorn machines (and other
machines) the "armv3", which will tie up with the new `uname -m` strings.

I would also strongly suggest calling the Netwinder (StrongARM with
half-word) the "armv4" since half-words are introduced into Architecture
V4, and is not allowed in V3 (if you believe the ARM architecture ref
manual).

This would then mean that we have a common base from which all the names
come from.

If anyone wants to know the exact strings that uname -m produces on
various machines, either look in the 2.1.xx source patches, or mail me
and I'll dig out the info.
   _____
  |_____| ------------------------------------------------- ---+---+-
  |   |        Russell King       [email-masked]      --- ---
  | | | |  http://www.arm.uk.linux.org/~rmk/armlinux.html    /  /  |
  | +-+-+                                                     --- -+-
  /   |               THE developer of ARM Linux              |+| /|\
 /  | | |                                                     ---  |
    +-+-+ -------------------------------------------------  /\\\  |

---

From: Jim Pick <[email-masked]>
Date: 29 Sep 1998 14:57:35 -0700

> machines) the "armv3", which will tie up with the new `uname -m` strings.

Agreed.
 
> V4, and is not allowed in V3 (if you believe the ARM architecture ref

I'll see what I can do.  We initially called it "arm" because we
didn't know any better (that was before the uname strings were settled
upon).  When I get some time, I'll talk to the maintainer of
ftp.debian.org to see what we can do about moving things around.
We'll also have to recompile all the stuff we've got so far to use the
new architecture names (not that big of a deal).
 
> This would then mean that we have a common base from which all the names

I agree that would be good.

Ok.

Cheers,

 - Jim

---

From: Russell King - ARM Linux Admin <[email-masked]>
Date: Tue, 29 Sep 1998 23:37:44 +0100 (BST)

> how fast the CATS hard drive was.  I'll have to give it a go.

Ok, after setting the PCI Latency timers to something sensible (32), I'm still
getting around 1.4MB/s.  There is the little matter of one of Phil's comments
lying around in the sources:

        /* Nobody could say these are optimal, but not to worry. */

Hmm, maybe I ought to optimise them then...

BTW, DMA doesn't seem to work with this drive (Conner CFS1081A) - does anyone
know if this drive is DMA capable?  According to hdparm -i:

 RawCHS=2097/16/63, TrkSize=0, SectSize=0, ECCbytes=4
 BuffType=0(?), BuffSize=0KB, MaxMultSect=16, MultSect=off
 DblWordIO=no, maxPIO=1(medium), DMA=yes, maxDMA=2(fast)
 CurCHS=2097/16/63, CurSects=2114180, LBA=yes, LBAsects=2114180
 tDMA={min:120,rec:120}, DMA modes: *mword0 mword1 mword2
 IORDY=on/off, tPIO={min:383,w/IORDY:120}, PIO modes: mode3 mode4

Anyone know what this means?  i'm guessing that it means that DMA mode 'mword0'
is supported, but none of the other modes.
   _____
  |_____| ------------------------------------------------- ---+---+-
  |   |        Russell King       [email-masked]      --- ---
  | | | |  http://www.arm.uk.linux.org/~rmk/armlinux.html    /  /  |
  | +-+-+                                                     --- -+-
  /   |               THE developer of ARM Linux              |+| /|\
 /  | | |                                                     ---  |
    +-+-+ -------------------------------------------------  /\\\  |
unsubscribe: body of `unsubscribe linux-arm' to [email-masked]

---

From: Russell King - ARM Linux Admin <[email-masked]>
Date: Tue, 29 Sep 1998 23:43:50 +0100 (BST)

> >I have is whether GCC will generate code which _won't_ run on a SA?

I thought that GCC can produce half-word instructions, which don't work
on the RiscPC.
   _____

---

From: Rob Davis <[email-masked]>
Date: Wed, 30 Sep 1998 08:15:58 +0100

In message <[email-masked]>

> > machines) the "armv3", which will tie up with the new `uname -m` strings.

Could you not simply put a symbolic link in the directory structure,
so that non-programmers could work out what to do.  The link
could be called acorn and link to the armv3 binaries?

-- 
Rob Davis                OAC Ministries, British Registered Charity, 295432
---------------------------------------------------------------------------
Homepage: http://www.oac.u-net.com    Mobile: 0973 359577 (SMS welcome)
[email-masked] (Rob.. At the house)
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---

From: Philip Blundell <[email-masked]>
Date: Wed, 30 Sep 1998 13:51:51 +0100

>could be called acorn and link to the armv3 binaries?

I think better would be to just mention in the documentation "if you have an 
Acorn machine, you need the armv3 distribution".

p.

---

From: Eduard Pfarr <[email-masked]>
Date: Wed, 30 Sep 1998 18:40:27 +0200

»Matthew Wilcox« schrieb in Artikel
<[email-masked]> folgendes:

> > The StrongARM has many pros compared to older ARMs (you know I know
> > <g>) so disabling the StrongARM features on Acorn StrongARM machines
> > »just« because they can't handle the halfword operations makes the
> > computers much slower than they should.
> 

Well, mea culpa when it comes to the relative term »much slower«. What is
much - and compared to what <g>.

Considering many Acorn user's experiences with C compiled programs on the
RiscPC when the StrongARM replaced the older ARMv3 CPUs: There's been a
performance difference when Acorn's C compiler became StrongARM aware. I
suppose this is mainly because the compiler addressed the improved cache
system (long cache lines maybe, alignment to 8 word boundary, etc) but I'm
unfortunately no compiler expert, just a programmer »brutus« <g>. RISC OS
3.7 has addressed these StrongARM features; again I suppose just because it
used a/the new compiler?

[..]
> there's a real problem before actually worrying about it.

AFAIK it's more the internal working (caching etc.) than new instructions.
Acorn's applications notes when the StrongARM CPU card has been released
mentioned some. Probably they're still on their server.

 Cheers,
 Eduard.

---

From: Matthew Wilcox <[email-masked]>
Date: Wed, 30 Sep 1998 18:58:50 +0200

> performance difference when Acorn's C compiler became StrongARM aware. I

Acorn have never shipped and do not possess a StrongARM-aware compiler.

---

From: Philip Blundell <[email-masked]>
Date: Wed, 30 Sep 1998 19:08:06 +0100

>BTW, DMA doesn't seem to work with this drive (Conner CFS1081A) - does anyone

What happens when you try to turn it on?  Some drives do seem to claim to be 
able to do DMA but actually fail every transfer if you use it.

> DblWordIO=no, maxPIO=1(medium), DMA=yes, maxDMA=2(fast)

It looks like the drive certainly thinks it supports DMA.  But the IDE driver 
almost certainly doesn't know about the cache coherency issues involved.

p.

---

From: Philip Blundell <[email-masked]>
Date: Wed, 30 Sep 1998 19:10:46 +0100

>I thought that GCC can produce half-word instructions, which don't work

Yes, it can, but I didn't think that was what Matthew was asking.  I took his 
question to mean "if I target GCC for an ARMv3 cpu, is there danger that the 
resulting code will fail on StrongARM".

The halfword problem on RiscPCs has had quite a substantial airing on this 
mailing list recently.

p.

---

From: Philip Blundell <[email-masked]>
Date: Wed, 30 Sep 1998 21:46:19 +0100

>Hmm, maybe I ought to optimise them then...

Having looked at the code again, although there certainly is some scope for 
improvement I don't think this is likely to be the direct cause of your 
problem.  My guess would be that the (presumably uncached) external I/O access 
will dominate the time taken for the transfer.  For routines like insw it 
really is important that those accesses happen 16 bits at a time so you can't 
use multiple-register load instructions either.

>From your hdparm settings it looks like you don't have 32-bit I/O enabled -- 
that would probably be quite a win as it will halve the number of these slow 
bus transactions.  That also has the advantage that you get to use the 
(apparently better optimised) insl rather than the slow insw.

You might also try turning on multiple-sector mode which also seems to be 
currently off.

p.