Subject: cache Flush is different from cache clean

From: "Neal. 03-Jul-1997 1810 +0100" <[email-masked]>
Date: Thu, 3 Jul 97 19:11:08 MET DST

>> > > liveable with and it's considerably better than your alternative
>> > > suggestion.
>> > 
>> > I diasgree. Not many CPUs need to do this and considerably worse, I can't
>> > think of any mainstream ones to hand...
>>
>> It is an extremely poor piece of design. The last thing you need to do on
>> a modern machine is load your bus down reading crap because the processor
>> lacks a very basic cache flush operation.
>>
>> On the P5 its about 10 clocks to flush the cache and no bus activity
>>
>> Alan

Hmm,

looks as though there is some confusion here. The SA-110 does not "lack a a very
basic cache flush operation" and there is NO software loop required to flush the
Dcache. Flushing the Dcache is performed by a single coprocessor instruction.

HOWEVER! The SA-110 Dcache is a writeback cache, unlike the caches in ARM
processors like the 610 and 710. What that means is that the Dcache may not be
coherent with main memory; it may contain a more-recent copy of cached data.
Therefore, before you flush the Dcache you need to *clean* it. This is the
process of evicting dirty data from the Dcache into system memory. It is the
cleaning operation that requires the software loop that has been mentioned. That
operation may require 16K or 32K reads depending upon what you read (reading
"crap" is optional).

This software read loop isn't the most impressive scheme for cleaning the cache
but it's not possible to do it with no bus activity - unless no entries in the
cache are dirty. As Dave said, these housekeeping chores are the price you pay
for the speedup that caches give you.

It's all explained in the SA-110 Technical Reference Manual, section 6.2.4.1 -
it's on our web page.

Neal. (EBSA-110 designer, 21285 memory controller designer)

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    Neal Crook
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