Subject: ROM access with 21285

From: David Aparicio Campos <[email-masked]>
Date: Wed, 24 May 2000 15:40:18 +0200

Hello all,

I am trying to develop a small firmware core, in order to load Linux
from
disk or network. At this first stage, we are concentrated on serial line

support and flash programming. We use a standard memory model, that is,
ROM mapped in range 0x41000000-0x41FFFFFF. I have also seen
very nice BIOS-ARM project (best to learn on this subject, helped me a
lot), but it doesn't focus on flash writing.

My development system is a CATS motherboard, and I have an SST29LE020
(256K x 8) flash, compatible with AMD 29xxx family. I succeed reading
flash
contents, but now I am trying to write and it doesn't work at all.

Simplest (and safest) test is to "read vendor ID" from flash device.
>From the SST
datasheet, I need to write three bytes, wait a few, read ID, then write
three bytes
to get back to normal mode.

SST datasheet says:

// enter ID-access mode
write byte offset 0x5555 to 0xAA
write byte offset 0x2AAA to 0x55
write byte offset 0x5555 to 0x90
...wait 10 ms...
then read byte from offset 0 (should say 0xBF)

// exit ID-access mode
write byte offset 0x5555 to 0xAA
write byte offset 0x2AAA to 0x55
write byte offset 0x5555 to 0xF0
...wait 10 ms...

285 datasheet is very dense on ROM writing, it's very difficult to me to
understand
it well. What I have interpreted is:

write 0x42000068 to (0x00005555 & 0x03)    // ROM write byte address
write 0x41005555 to 0xAA
write 0x42000068 to (0x00002AAA & 0x03)    // ROM write byte address
write 0x41002AAA to 0x55
write 0x42000068 to (0x00005555 & 0x03)    // ROM write byte address
write 0x41005555 to 0x90
wait  10 ms
read  0x41000000 (it says 0x00 instead of 0xBF)
...etc, etc...

It doesn't work, I read the same value that I have in normal mode
(0x00). Can anybody
tell me if I need to write any 285 register? what am I doing wrong?
I have seen some references from NetWinder code, but it's useless
because it uses an
Intel flash, that is less restrictive with write sequences, so I didn't
get any idea.

I got no support from Chaltech, and CD documentation is very poor, real
nightmare to get
support for this product, maybe I had bad luck, but
"[email-masked]" seem to be
out of order.

Is there any documentation on this motherboard?

Thank you a lot,

---

From: Nicolas Pitre <[email-masked]>
Date: Wed, 24 May 2000 10:39:29 -0400 (EDT)

> I am trying to develop a small firmware core, in order to load Linux from
> disk or network. At this first stage, we are concentrated on serial line support and flash programming. We use a standard memory model, that is,
> (256K x 8) flash, compatible with AMD 29xxx family. I succeed reading flash

If your flash is wired 8-bit or 16-bit wide to the 21285, then you have to
play some trick with the CSR_ROMWRITEREG register to address each
individual byte or halfword.

Here are the sequence to perform if your flash data bus is 8-bit wide:

Addr to write to	Sequence
0x41000000:		*CSR_ROMWRITEREG = 0;  *((u_long*)0x41000000) = x;
0x41000001:		*CSR_ROMWRITEREG = 1;  *((u_long*)0x41000000) = x;
0x41000002:		*CSR_ROMWRITEREG = 2;  *((u_long*)0x41000000) = x;
0x41000003:		*CSR_ROMWRITEREG = 3;  *((u_long*)0x41000000) = x;
0x41000004:		*CSR_ROMWRITEREG = 0;  *((u_long*)0x41000004) = x;
0x41000005:		*CSR_ROMWRITEREG = 1;  *((u_long*)0x41000004) = x;
0x41000006:		*CSR_ROMWRITEREG = 2;  *((u_long*)0x41000004) = x;
0x41000007:		*CSR_ROMWRITEREG = 3;  *((u_long*)0x41000004) = x;
0x41000008:		*CSR_ROMWRITEREG = 0;  *((u_long*)0x41000008) = x;
0x41000009:		*CSR_ROMWRITEREG = 1;  *((u_long*)0x41000008) = x;
... and so on.

For halfword, only the first bit should be specified by CSR_ROMWRITEREG.

If your flash is accessed 32-bit wide, all this doesn't apply.

Nicolas

unsubscribe: body of `unsubscribe linux-arm-kernel' to [email-masked]

---

From: David Aparicio Campos <[email-masked]>
Date: Wed, 24 May 2000 18:41:45 +0200

> 0x41000000:             *CSR_ROMWRITEREG = 0;  *((u_long*)0x41000000) = x;

Ok. It's a 8-bit wide. In fact I was using a macro like this:

ROMWRITE(OFFS, VAL):
    *CSR_ROMWRITEREG = (OFFS&3);
    *((volatile u_char *)(0x41000000 + OFFS));

But what I was doing bad was address bits 0 and 1 for ROM space need to be
cleared like this (it seems to me than datasheet doesn't specify this):

ROMWRITE(OFFS, VAL):
    *CSR_ROMWRITEREG = (OFFS&3);
    *((volatile u_char *)(0x41000000 + (OFFS & 0xFFFFFC)));

It's working!!. Thank you very much, Nicolas.

  David

---

From: [email-masked] (Erik Mouw)
Date: Wed, 24 May 2000 19:19:06 +0200 (CEST)

> lot), but it doesn't focus on flash writing.

Have a look at blob, the LART bootloader. All the basic functionality is
already in place, you just have to modify it for your board. URI:

  http://www.lart.tudelft.nl/lartware/blob/

Erik

-- 
J.A.K. (Erik) Mouw, Information and Communication Theory Group, Department
of Electrical Engineering, Faculty of Information Technology and Systems,
Delft University of Technology, PO BOX 5031,  2600 GA Delft, The Netherlands
Phone: +31-15-2783635  Fax: +31-15-2781843  Email: [email-masked]
WWW: http://www-ict.its.tudelft.nl/~erik/