Subject: StrongARM cache coherency and EtherExpress NICs

From: Chris Bohme <[email-masked]>
Date: Mon, 22 Nov 1999 20:02:21 +0200 (SAT)

Hi all,

I am trying to get Intel EtherExpress (82558/9) cards to work with the 
EBSA285. From the driver code it does not seem as if cache coherency is 
addressed.

Has anyone implemented these cache fixups for the eepro100 driver ?

And another question, if the cache is to be off, where should this be 
done ? I tried turning it off in kernel/head-armv.S, but that did not 
seem to have any effect (is it re-enabled later on ?)

Thanks,

Chris  

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From: David Sean Friedman <[email-masked]>
Date: Wed, 24 Nov 1999 12:21:22 -0500 (EST)

Excerpts from arm-linux: 22-Nov-99 StrongARM cache coherency a.. by
Chris [email-masked] 
> Has anyone implemented these cache fixups for the eepro100 driver ?
My group has a patch for this, but the driver has a few problems, which
probably are not ARM related. Check the mailing list archives for
linux-eepro100 at tux.org for a full discussion. Supposedly, the latest
driver fixes these problems for most people.

> seem to have any effect (is it re-enabled later on ?)
This is the way we used to disable the cache. I don't have a tree with
Russell's patch in front of me, but we used to change a line that looked
like this in the label .Larmv4_flush_early:
orr     r0, r0, #0x003d                         @ I...S..DPWC.M

so that it would disable the data cache and write buffers (I think those
are the C and W bits).

If you are interested in our patch, let me know. We used the eepro100
with an ebsa285 and intel 82557/8.

David Friedman
Carnegie Mellon

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From: Jonathan Kliegman <[email-masked]>
Date: Wed, 24 Nov 1999 13:57:49 -0800

> with an ebsa285 and intel 82557/8.

I remember that there was a second problem with disabling the cache.  If
'CONFIG_KERNEL_ALIGNMENT_TRAP' (or something similar, I don't have a
tree in front of me) is turned on then there is a variable (whose name
escapes me) which stores the user mode state.  On context switches the
MMU is updated based in part on this variable.  If you search for the
tree for the MCR and MRC instructions you should be able to find it.  

Sorry I'm not being more helpful - I haven't had time to look/play with
a kernel tree in a while...

-Jon

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From: Russell King - ARM Linux Admin <[email-masked]>
Date: Wed, 24 Nov 1999 22:05:20 +0000 (GMT)

> tree for the MCR and MRC instructions you should be able to find it.  

It's called cr_alignment, which is initialised from the mov instruction
in arch/arm/mm/proc-*.S (via head-armv.S).  Therefore, disabling the cache
in arch/arm/mm/proc-*.S will disable the cache while Linux is running in
total.  (It's done this way since you can't guarantee that you can read-
modify-write the control register, and the control register value is
processor specific).
   _____
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